PCIe ASIC Design Engineer

About the role

Cornelis Networks is seeking a Senior ASIC Design Engineer to lead the design and integration of PCIe controllers into our next-generation SoCs. The ideal candidate will have deep expertise in PCI Express protocol (Gen4/Gen5/Gen6), integration into high performance ASICs, emulation and post silicon bring-up.

Responsibilities

• Own end-to-end integration of PCIe IP into complex ASIC designs.
• Collaborate with IP vendors, architecture, verification, physical design, and software teams to deliver robust PCIe subsystems.
• Drive performance optimization efforts across the PCIe stack, from PHY tuning to DMA/transaction layer efficiency.
• Contribute to system architecture and microarchitecture discussions with a focus on IO and interconnect scalability.
• Lead silicon bring-up and validation of PCIe links in the lab; work closely with board and firmware teams.
• Debug functional and performance issues at RTL, gate-level, and silicon.
• Ensure compliance with PCIe specifications and participate in interoperability testing where needed.
• Provide mentorship to junior engineers and help define PCIe subsystem development best practices.

Requirements

• Good understanding of high-bandwidth, low-latency connectivity for high-performance compute platforms.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in ASIC/SoC design with a focus on PCIe controller integration.
• Proven experience in silicon bring-up and debug of high-speed interfaces.
• Solid understanding of PCIe protocol stack (PHY, MAC, TLP, DLL), configuration space, and link training.
• Hands-on experience with PCIe verification environments, performance tuning, and power-aware design.
• Familiarity with PCIe compliance testing, simulation tools (e.g., VCS, Questa), and lab equipment (e.g., protocol analyzers, oscilloscopes).
• Strong scripting (Python, Perl, TCL) and debugging skills.
• Strong verbal and written communication skills.

Preferred Qualifications

• Experience with PCIe Gen5/Gen6 and advanced retimer or switch solutions.
• Exposure to CXL, CCIX, or other cache-coherent interconnects.
• Background in data center or AI/ML accelerator architectures.
• Experience with emulation and prototyping platforms (e.g., ZeBu, Palladium, HAPS) for PCIe subsystem validation.

Pay

Competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits.

Schedule

This is a remote position for employees residing within the United States.