Jobs · Engineering · California

Package Design Engineer

Broadcom · San Jose, CA · 4 days ago
EngineeringFull-time

About the role

Broadcom is seeking an experienced IC package-design engineer for complex flip-chip-BGA packages for industry-leading ASICs with high-speed SerDes and very-high-power delivery needs. You will be part of a worldwide R&D team developing high-performance package designs for ASICs for artificial intelligence (AI), networking, high-performance computing (HPC), and 5G base stations. These designs include SerDes at 224G and higher, 5G RF/Microwave ADC/DAC, HBM, DDR5 and more.

Responsibilities

  • Overall design responsibility for ASIC package designs, including aspects of signal integrity, power integrity, manufacturability, reliability, and thermal, in partnership with our experienced team of package engineering experts.
  • Package design of critical structures for SerDes, ADC/DAC, DDR, etc.
  • Schedule, prioritize, and track your work across 2+ projects simultaneously.
  • General flip-chip BGA package design and engineering.
  • Project management and customer interface for your design projects.
  • Contribute to efficiency improvements for the design team, through process development/improvement, automation, documentation, etc.
  • Physical design (layout) is a foundational responsibility in this role.

Requirements

  • BSEE or similar field and 8+ years’ experience in flip-chip-BGA package design, including high-speed SerDes or MSEE or similar field and 6+ years’ work experience.
  • Knowledge of package-level signal integrity and power integrity, to apply to package designs.
  • Cadence APD (Allegro Package Designer) experience is preferred. Equivalent tool is acceptable.
  • Ability to cooperate with a worldwide team (multiple time zones), including co-design with internal team members and external (vendor) designers.
  • Strong self-management and organization skills.
  • This job requires working on-site at the Broadcom office, 5 days a week. This is not a remote-work position.

Preferred Qualifications

  • 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest.

Pay

The annual base salary range for this position is USD 121,900.00 to USD 195,000.00.

Benefits

  • Discretionary annual bonus.
  • Competitive new hire equity grant and annual equity awards, subject to relevant plan documents and award agreements.
  • Medical, dental, and vision plans.
  • 401(K) participation including company matching.
  • Employee Stock Purchase Program (ESPP).
  • Employee Assistance Program (EAP).
  • Company-paid holidays, paid sick leave, and vacation time.
  • Paid Family Leave and other leaves of absence, in accordance with applicable laws.

Similar jobs

Packaging Design Engineer

MillenniumSoft IncFranklin Lakes, NJ· 25 mo ago
Engineeringapply on millenniumsoft.applicantstack.com