Package Design Engineer

About the role

You will work closely with IP, SoC Design, Package Design, Signal/Power Integrity, and Systems teams throughout the company, as well as interact with leading worldwide technology partners. This opportunity focuses on multichip systems where 2.xD and 3D approaches are necessary for optimizing performance in emerging system-level solutions for Arm’s world-class IP ecosystems.

The job will be based out of San Jose, CA or Chandler, AZ.

Responsibilities

• Draw novel System-in-Package designs using state-of-the-art power delivery techniques and interfaces.
• Define, design, and verify package designs for emerging technologies.
• Collaborate with teams in France, the US, the UK, and other Arm locations as needed.
• Work closely with digital designers (P&R) to establish inputs and constraints for efficient designs.
• Interact with Signal Integrity/Power Integrity (SI/PI) engineers.
• Communicate clearly with team members and adapt to loosely defined problems and changing requirements.

Requirements

• Engineering degree or equivalent.
• 5 or more years of experience in package design.
• Understanding of signal/power integrity principles to optimize designs.
• Proficiency in package drawing tools (Cadence APD/SiP/Allegro or equivalent).

Nice-to-Have Skills

• Experience with larger LPDDR and DDR interfaces.
• Experience with 2.xD and 3D package systems.