Member of Technical Staff, ASIC Design

About the Role

We are seeking experienced Senior ASIC Designers to join an early-stage startup working on an exciting product in the Artificial Intelligence/DataCenter space. The role demands proven technical expertise in advanced ASIC design flows, leadership in execution, cross-functional coordination, and final product delivery. You will focus on designing memory acceleration for advanced LLM applications in modern data centers. This is an onsite position based in either Santa Clara, CA or Boston, MA.

Responsibilities

• Lead RTL design of IPs, subsystems, and SOCs supporting the company’s silicon roadmap.
• Provide technical leadership in defining IP/SOC microarchitecture specifications and design methodologies.
• Conduct design reviews to ensure adherence to best practices.
• Guide the team in optimizing designs to meet aggressive performance, power, and area (PPA) goals using advanced architectural and design techniques.
• Drive collaboration with partner teams across architecture, verification, physical design, firmware, DFT, and post-silicon domains to ensure successful system-level functionality.
• Interface with external IP vendors, foundries, and EDA tool providers to address dependencies and roadblocks in a timely manner.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• Minimum of 5+ years of ASIC/SOC digital design experience.
• Strong leadership, communication, team-building, and stakeholder management skills.
• Ability to coordinate across multiple projects, manage risks, and work under tight schedules and budget constraints.
• Strong knowledge of the full ASIC/SOC development cycle from microarchitecture to tape-out in advanced process technologies.
• Expertise in microarchitecture development, RTL coding (Verilog/SystemVerilog), synthesis, STA/timing closure, physical design, and verification methodologies.
• Hands-on design experience with industry-standard protocol stacks such as Ethernet, UCIe, or UALink.
• Demonstrated ability to optimize designs for PPA and integrate major subsystems (interconnect, I/O, memory).
• Proficiency with front-end development tools/methodologies and scripting for automation and flow integration.
• Design and tapeout of advanced silicon devices is highly preferred.

Preferred Qualifications

• PhD in Electrical Engineering, Computer Engineering, or a related field.
• Experience managing relationships with external design partners, IP vendors, and foundries.
• Knowledge of Design-For-Testability (DFT), post-silicon debug/validation, and manufacturing test.

Benefits

• Competitive salary including base pay, performance-based bonus, and early-stage equity grant.
• Comprehensive benefits: health, dental, vision, and life insurance.
• Well-equipped, sunny offices in Santa Clara, CA and Boston, MA.
• Relocation assistance and visa sponsorship.
• Perks: daily lunch stipend, 401k match, and more.
• Collaborative, continuous-learning work environment with smart, dedicated colleagues.

About the Opportunity

• Impact: Tackle a fundamental challenge at the infrastructure layer: unlocking greater AI capability while dramatically improving efficiency. Your work will compound across state-of-the-art AI models, systems, and real-world applications.
• Timing: Join now for real ownership of the company and meaningful influence over product direction and execution. Work from first principles, move quickly from insight to execution, and see your contributions directly reflected in the product.
• Culture: Work alongside a team that values rigor, clarity, and impact. Thoughtful disagreement, fast learning, and intellectual fearlessness are encouraged. Growth is a daily practice.