Manager, Package Design Engineering

Key Responsibilities

• Team Leadership & Execution
• Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows
• Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs
• Lead design reviews, audits, and issue resolution through bring-up and production ramp
• Package Design Delivery
• Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production
• Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
• Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery
• Cross-Functional Collaboration
• Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges
• Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps
• Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms
• Methodology & Automation
• Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization

Basic Qualifications

• Bachelor's degree in Electrical Engineering, Materials Science, or related field
• 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP
• 5+ years of leadership experience managing teams or technical organizations in IC packaging environments
• Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool
• Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)
• Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals
• Proven experience working with OSATs and substrate vendors through development and production ramp

Preferred Qualifications

• Master's degree in Electrical Engineering or related field
• Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration
• Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization
• Background in early package feasibility, platform evaluation, and technology roadmap development
• Familiarity with chip floor planning, architecture, and system-level tradeoffs
• Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations