Lead Memory Controller Micro-Architect

Position Summary

Samsung, a world leader in advanced semiconductor technology, seeks a Lead Memory Controller Micro-Architect to join the Samsung Austin Research and Development Center (SARC) and Advanced Computing Lab (ACL). This role involves leading the design and development of Samsung's advanced memory controllers, including LPDDR5, LPDDR6, PIM, and future DDR5, GDDR7, and HBM4. The ideal candidate will have extensive experience in memory controller micro-architecture and RTL design, translating innovative concepts into cutting-edge memory technologies.

Role And Responsibilities

• Lead the design and development of Samsung's advanced memory controllers (LPDDR5, LPDDR6, PIM, and beyond).
• Translate innovative concepts into next-generation memory technologies that drive Samsung's leadership in the field.
• Own and influence the entire memory controller microarchitecture, including RTL design and performance/power optimization.
• Collaborate with cross-functional teams to ensure design functionality, meet PPA goals, and resolve implementation challenges.
• Ensure design quality through LINT, CDC, ECO flows, power analysis, and other methodologies.

Skills And Qualifications

• 20+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 18+ years with a Master’s Degree, or 16+ years with a PhD.
• Proven experience in memory controller micro-architecture and RTL design, owning all sub-blocks of custom memory controller designs.
• Deep expertise in multiple memory technologies, such as LPDDR4/5/6, PIM, DDR, GDDR, and HBM.
• Strong knowledge of JEDEC memory standards and working knowledge of DDR PHY.
• Demonstrated success in driving architecture through RTL design for high-performance digital systems.
• Strong expertise in Verilog and ASIC design flow, including RTL design, verification, synthesis, timing analysis, and ECO.
• Proficiency in scripting languages (Perl, Python) to support design and automation.
• Strong communication and collaboration skills; Ability to navigate ambiguity in a fast-paced, global team environment.
• Familiarity with interface protocols (AMBA, AXI, ACE) is desired.
• Knowledge of AES, ECC, and RAS features is preferred.
• Self-driven, curious, and passionate about logic design and innovation.

Total Rewards

• Base pay range: $221,700 - $364,800.
• Eligible for MBO bonus compensation, based on company, division, and individual performance.
• Participation in long-term incentive plan and relocation.