CPU Micro-architect

Position Summary

Samsung, a world leader in advanced semiconductor technology, is seeking a talented CPU Micro-architect to join its team. This role involves exploring new features and optimizing the microarchitecture of high performance Out-of-Order (OOO) CPU cores, collaborating with cross-functional teams, and pushing the boundaries of processor design.

Role And Responsibilities

• Explore new features and optimize the microarchitecture of high performance OoO CPU cores.
• Collaborate with cross-functional teams and external partners to push the boundaries of processor design.
• Improve the benchmarks and real-use-case performance (IPC, power/area efficiency) of a state of the art (SOTA) OoO CPU core, covering all aspects of the micro-architecture, including core pipelines, branch prediction, prefetching, and cache/TLB hierarchy.
• Work with the performance simulation team to model the microarchitecture of the SOTA core.
• Correlate simulation results against silicon measurement data, and perform thorough root cause analysis and debugging to identify, diagnose, and rectify any discrepancies, ensuring model accuracy and reliability.
• Explore new features and ISA extensions (e.g., vector extensions, memory safety features, security enhancements, etc.) to drive performance enhancements, optimizing efficiency, reliability, and protection.
• Identify and resolve performance bottlenecks through modeling and prototyping.
• Develop performance models (as needed) and micro testbenches to improve and validate key performance features in the CPUs.
• Collaborate with cross-functional teams and external partners to ensure seamless integration of designs.

Skills And Qualifications

• 10+ years of experience with a Bachelor’s Degree in Computer Science/Engineering, or 8+ years of experience with a Master’s Degree, or 6+ years of experience with a Ph.D.
• Extensive background in CPU microarchitecture design, with a strong understanding of computer architecture principles, including pipelining, superscalar design, cache hierarchies, coherency, and multi-core systems.
• Strong experience in performance analysis, modeling, and optimization, as well as common mobile benchmarks like GB6 and SpecInt17, and real use cases such as games and web browsing.
• Familiarity with Arm ISA (Armv8/v9) and extensions, or equivalent ISAs (x86 and RISC-V), and their impact on microarchitecture.
• Proficiency in reading – and writing as needed – hardware description languages (Verilog/SV) and programming languages (C++, Python) for modeling and simulation.
• Able to correlate simulation performance results against hardware performance metrics (cache misses, TLB misses, pipeline stalls) to ensure optimal performance.
• Excellent problem-solving skills and the ability to work in a collaborative, interdisciplinary environment.

Total Rewards

• Base pay range: $151,000 - $251,800
• Benefits: Medical, dental, vision, life insurance, 401(k), onsite lunch, employee purchase program, tuition assistance (after 6 months), paid time off, student loan program, wellness incentives, and more.
• MBO bonus compensation, long term incentive plan, and relocation eligibility.
• This is an exempt position, which is not eligible for overtime pay under the Fair Labor Standards Act (FLSA).