CPU Micro-Architect / RTL (Lead & IC Engineers)

About the role

As a CPU Micro-Architect/RTL Engineer on Nuvacore's CPU team, you will write specifications and develop RTL for a ground‑up high‑performance, low‑power CPU targeting next‑generation compute workloads. You will lead CPU units such as fetch, decode/rename, scalar execute, fp/vector execute, load/store, memory management/TLB, prefetching, debug/trace, system/IO, and multi‑level cache subsystem.

Responsibilities

• Micro‑architecture development and specification – start from a performance‑driven design strategy, work with the performance modeling team to study early micro‑architectures and converge on a detailed specification; understand pipelines and intra‑unit communication to build a clean, performant design.
• RTL design – develop and refine RTL that meets power, performance, area and timing goals; apply modern Verilog standards to create flexible, robust, configurable, scalable code.
• Verification – assist the verification team with testbench development, formal methods, simulation/emulation for formal verification.
• Performance exploration and correlation – explore high‑performance strategies and collaborate with the performance architecture and verification team to verify that RTL meets targeted performance.
• Physical design – work with the PD engineering team to implement and verify physical design meets goals; iterate and refine RTL for timing, power, area, DFT, and reliability.

Requirements

Must‑have

• BS or MS with 15+ years experience (leads) or 7+ years experience (ICs) in high‑performance, low‑power CPU design.
• Experience coding in Verilog, debugging, simulation; ideally with experience driving modern AI tools to assist in RTL coding.
• Solid understanding of logic and physical design and their impacts on timing, power, and area.
• Experience with RISC‑V, ARM64, or x86 ISA and their impacts on CPU micro‑architectural choices.

Nice‑to‑have

• Expertise in one or more of: instruction fetch, branch prediction; instruction decoding, scheduling and register renaming; out‑of‑order execution; integer and floating point execution; load/store execution; prefetching; cache and memory subsystems; translation and memory management; memory coherence and ordering; power and thermal management; clocking / reset design.
• Strong background in low‑power microarchitecture and high‑performance design techniques, with a proven track record on multiple CPU programs/products.
• Experience in C, C++, and other languages such as Perl or Python.