Technical Director Memory Controller Architect

Responsibilities

• Own the architecture specification for Rambus memory controllers
• Work closely with product management, product marketing, technical field organization and customers to understand feature priorities and market needs
• Work closely with logic design, verification and physical design teams to define implementation-friendly, high performance and PPA optimized products and realistic timelines
• Actively drive technical reviews including implementation review, verification review, PRD/ERD review
• Represent the Rambus SIP team at JEDEC standards body
• Work closely with system modeling team to explore and finalize next generation architectures
• Collaborate with Rambus Labs research team to incorporate innovative and differentiated features to establish clear leadership
• Protect Rambus innovations through patent disclosures
• Evangelize Rambus memory controller products through technical publications and industry events
• Empower field teams through product training in collaboration with marketing and product management teams

Qualifications

• BS/MS with 20+ years’ experience in semiconductor industry, with at least 10 years on memory logic design and/or architecture
• IP experience is preferred
• Hands-on experience with RTL coding, logic design, physical design and DV techniques
• Knowledge of HBM, LPDDR and AXI protocols and controllers
• GDDR and CHI protocol knowledge will be a plus
• Knowledge of front-end ASIC development flow and best practices
• Knowledge of system architecture for HPC and AI systems, including impact to memory controller architecture
• Strong verbal and written communication skills and the ability to work in a fast-paced environment
• Excellent soft skills and collaborative mindset to work with cross functional teams
• Able to make timely decisions based on available data
• Technical presales experience is desirable