Lead Hardware Design Validation Engineer

NVIDIA · Santa Clara, CA · 3 mo ago

EngineeringFull-time

Join NVIDIA's groundbreaking team as a Lead Hardware Design Validation Engineer for our GPU, datacenter and automotive platforms in Santa Clara, CA!

Own end-to-end product validation from architecture/design phase, through bring-up to mass production: set strategies, define test plans, and track progress to ensure the product meets spec and ships successfully.
Lead and mentor design validation engineers.
Guide related validation teams (thermal, EMI, reliability, etc.) and partners (such as JDM) through the validation cycles.
Represent design validation in executive and cross-functional product reviews and debug forums.
Be the accountable technical owner for validation status, risks, and different milestones/release readiness.
Define test plans across the full system based on product design, such as power, high-speed IO, low-speed IO, clock/resets, manageability (BMC), sensors, telemetry, firmware, full-system functional/stress validation etc.
Guide manufacturing test approaches; contribute to production troubleshooting and boosting yield.
Collaborate with and lead vendors and partners to complete validation activities.
Drive system-level debugging and root cause analysis on complex issues (including critical field returns) spanning silicon, board, system, signal integrity, firmware, and software.
Influence product design through design review and validation/debug feedback.
Build scalable validation automation and lab infrastructure across product lines.

BS+ in EE/CE or equivalent experience.
8+ years of related experience with a proven track record as a technical lead for a shipping hardware product.
Proven leadership, leading validation through an entire product cycle from bring-up to mass production.
Strong system troubleshooting skills covering silicon, board, SI, firmware, OS, and applications.
Hands-on experience with power validation, including PDN, power regulators, sequencing, telemetry, protection etc.
Expertise in high-speed IO functionality and electrical validation, such as PCIe, SerDes, Ethernet, USB, or display.
Proficient in low-speed IO functionality and electrical validation, including I2C, SPI, UART, JTAG, SMBus, reference clock, etc.
System functional and stress test experience: define and complete system-level stress workloads (thermal, power, IO, memory, mixed-mode, corner V/F, Wide Area Test etc.) to expose marginality and uncover corner-case failures.
Proficiency with lab equipment and scripting, comfortable in Linux environments including driver/firmware debug with strong communication and program management skills; able to lead across multiple teams, sites, and time zones.
Experience with manufacturing test plans, collaborating with OPs/CM/OEM teams, and driving production debug and yield improvement.
Able and willing to travel internationally (primarily to Asia mfg sites such as Taiwan, China mainland etc.), up to 8% during NPI peak, to support builds.

Willing to go to local manufacturing sites near Santa Clara (typically up to 5%) to support NPI builds and un-gate factory.

Experience leading validation for a GPU, server, automotive platform, or AI accelerator from first silicon to mass production.
Datacenter platform experience: high-density/rack-scale power, liquid cooling (CDU, manifolds, leak detection), manageability (BMC) etc.
Proven capability in managing or technically leading a team of validation engineers.
Able and willing to travel internationally (primarily to Asia mfg sites such as Taiwan, China mainland etc.), up to 8% during NPI peak, to support builds.

Comprehensive benefits package.
Competitive salaries based on location, experience, and the pay of employees in similar positions.
Eligibility for equity.

Base salary range is 168,000 USD - 258,750 USD for Level 4, and 200,000 USD - 322,000 USD for Level 5.

Applications for this job will be accepted at least until June 12, 2026.

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