Lead Digital ASIC Design Engineer

About the role

K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors and an additional $500M in signed contracts, we’re mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. We are seeking a highly skilled Lead Digital ASIC Engineer to drive the design and implementation of digital subsystems for advanced wireless SoCs along with managing a team of ASIC design engineers. You will work as part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space.

Responsibilities

• Lead and manage a team of digital design engineers, providing technical mentorship, career development, and performance management.
• Manage development schedules, track deliverables, and report status to senior leadership and cross-functional teams.
• Contribute to design and implementation of microarchitecture and RTL for key digital blocks in wireless SoCs, including DSP systems, interfaces, and control logic.
• Collaborate with system architects to translate high-level DSP algorithms and chip specifications into efficient hardware implementations.
• Develop RTL for complex digital subsystems such as filters, beamformers, FFT/IFFT engines, and digital front-ends.
• Contribute to design and integration of digital blocks for interfaces, power management, clocking, reset, test, and debug infrastructure.
• Work with analog/mixed-signal teams to define and implement digital-analog interfaces, calibration engines, and control logic.
• Optimize designs for power, performance, and area (PPA) while meeting timing, area, and power constraints.
• Collaborate with synthesis and backend teams to achieve timing closure and resolve design issues.
• Contribute to verification planning and work closely with verification teams to validate complex digital subsystems.
• Participate in chip bring-up and lab validation activities for digital subsystems.
• Support products through production and spaceflight operations.
• Mentor junior engineers and contribute to team technical growth and best practices.

Qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of industry experience in digital ASIC design with ownership of complex digital blocks or subsystems.
• 3+ years of experience leading ASIC design teams or projects, including mentoring engineers and managing deliverables.
• Strong proficiency in RTL design using SystemVerilog or Verilog, with experience in synthesis and linting tools.
• Experience in microarchitecture definition and implementation based on architectural guidelines and analysis.
• Hands-on experience with timing closure, working effectively with synthesis and static timing analysis teams.
• Familiarity with DFT concepts and tools for scan and BIST insertion.
• Solid understanding of SoC design flows including clock/power domain crossing, timing constraints, and verification methodologies.
• Experience with DSP blocks for wireless communication systems (e.g., OFDM, MIMO, channel estimation, DFE).
• Proficiency with industry-standard EDA tools for design, synthesis, static timing analysis, and power analysis (e.g., Synopsys, Cadence, Siemens tools).
• Strong debugging, problem-solving, and communication skills with ability to work effectively in cross-functional teams.

Skills

• Experience in wireless SoC development (e.g., cellular, Wi-Fi, satellite, or mmWave systems) with successful tapeouts.
• Design experience with datapath architectures, flow control, arbitration, FIFO, DMA, IOMMU, and SoC bus architectures.
• Experience with ARM's AXI/AHB bus architectures and protocols, and serial interfaces such as SPI, I3C, UART.
• Familiarity with DSP algorithm modeling using MATLAB, Python, or C++ and converting models into RTL implementations.
• Experience working with FEC, baseband PHYs, or digital beamforming architectures.
• Knowledge of digital calibration and control of RF/mixed-signal front ends.
• Exposure to hardware-software co-design and embedded processor integration.
• Experience working in fast-paced startup or cross-functional, geographically distributed teams.

Pay

Base salary range for this role is $200,000 – $300,000 + equity in the company. Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level.

Benefits

• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.
• Many other perks.

Export Compliance: The person hired for this role must be a “U.S. person” as defined by 22 C.F.R. 120.15 or otherwise eligible for a federally issued export control license.