Lead Analog Design Engineer (Principal)

Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

About the Role

As a Principal Analog Design Engineer with Marvell, you’ll be a lead member of the Central Engineering business group. Central Engineering provides the most advanced and key analog IPs to all businesses within Marvell, including Data Center, Networking, and Connectivity. You’ll be part of a key analog team that makes an outsized impact on the technological arc of innovation in the field of High Speed SerDes Links.

We are seeking a Mixed Signal Lead to be part of a key team designing highly sophisticated electrical/optical wireline transceiver/SerDes for datacenter connectivity. Responsibilities span architectural investigations and implementation for circuits such as PLL, DLL, ADC, CTLE, regulators, amplifiers, TX, RX, CDRs, etc., to meet key performance targets, and performing design verification using industry-standard tools such as SPICE, Spectre, MATLAB, etc.

As a Lead Analog Circuit Design Engineer, you will collaborate with system architects and a global team of circuit and physical designers to build best-in-class electrical/optical serial links for AI-driven datacenter connectivity solutions. Your work will swing between research and development geared toward circuits at the bleeding edge of technology and data rates, and hands-on ("roll-up-the-sleeve") design of circuits for advanced wireline links.

Responsibilities

• Architectural investigations and implementation of analog circuits such as PLL, DLL, ADC, CTLE, regulators, amplifiers, TX, RX, CDRs, etc.
• Perform design verification using industry-standard tools (SPICE, Spectre, MATLAB).
• Collaborate with system architects, layout/physical design, digital design, and validation teams for the successful development, release, and support of complex mixed-signal IPs.
• Supervise analog layout in deep submicron technologies to achieve key performance targets for high-speed design.
• Develop and drive test plans to support validation for the full cycle development of IPs and products.

Requirements

• Completed MS or PhD in Electrical Engineering with 5-10 years of related experience.
• Expertise in one or more of the following focus areas of analog design: ADC/DACs, Front-Ends, CTLE, PLL, Timing circuits, CDRs, SerDes.
• Strong knowledge of deep sub-micron CMOS technologies.
• Keen eye for analog layout in latest deep submicron technologies.
• Excellent problem-solving and analytical skills to tackle circuit design challenges.
• Excellent debug skills to support validation and test plans.

Pay

Expected base pay range: $174,530 - $261,400 per annum. The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location, and market conditions.

Benefits

Marvell is committed to providing exceptional, comprehensive benefits that support employees at every stage—from internship to retirement and through life’s most important moments. Our offerings include:

• Employee stock purchase plan with a 2-year look back.
• Family support programs to help balance work and home life.
• Robust mental health resources to prioritize emotional well-being.
• Recognition and service awards to celebrate contributions and milestones.

This position may require access to technology and/or software subject to U.S. export control laws and regulations. Applicants must be eligible to access export-controlled information as defined under applicable law.