IP Enablement Application Engineer

Intel Foundry is a systems foundry dedicated to transforming the global semiconductor industry by delivering cutting-edge silicon process and packaging technology leadership for the AI era. With a focus on scalability, AI advancement, and shaping the future, we provide an unparalleled blend of industry-leading technology, a rich IP portfolio, a world-class design ecosystem, and an operationally resilient global manufacturing supply chain.

About the role

The Aerospace, Defense & Government (ADG) IP Enablement Application Engineer provides comprehensive technical support to Intel Foundry Services customers on IP integration challenges. This dynamic role requires a versatile engineer who engages with IP design teams and internal/external customers across all phases of IP development—from architecture through post-silicon validation and debug. The position embodies customer obsession by quickly resolving issues and providing hands-on debug across all design domains.

Responsibilities

• Provide comprehensive technical support to Intel Foundry Services customers on IP integration issues, working independently with design teams and customers to solve complex challenges remotely or onsite.
• Fully own assigned IPs and work with internal and external customers to help them integrate Intel IPs into SoCs, providing expert technical support throughout the integration process.
• Drive resolution of customer issues related to IP collaterals generation, logic design verification, IP release, and integration in SoC environments.
• Work with cross-functional teams to develop SoC and IP integration methodologies and best practices.
• Engage with IP development teams to ensure all IP collaterals are generated and provided according to customer requirements and industry standards.
• Collaborate with internal teams across Intel and external stakeholders including foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution.
• Engage in upfront identification and documentation of customer requirements, working with IP design teams to disposition and address requests.
• Prepare comprehensive customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug.
• Create application notes, documentation, and deliver technical training presentations to customers and internal teams.
• Drive quality improvements in design kits and documentation, assisting in removing barriers to successful customer design tape-outs.
• Support debugging and problem-solving activities in collaborative team environments.
• Contribute to methodology improvements that enhance IP integration productivity and customer satisfaction.

Requirements

• US Citizenship required.
• Ability to obtain a US Government Security Clearance.
• Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study.
• 2+ years of experience in SOC IP Integration.
• 3+ years of combined experience in RTL design and DFT using Verilog/System Verilog.
• Experience in ASIC or SoC development.

Qualifications

• Active US Government Security Clearance with a minimum of Secret level.
• Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study.
• Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.).
• Experience with VCS, Verdi, Spyglass or equivalent tools.
• Experience with IP integration and design flow challenges within the context of subsystems and SOCs.
• Experience with IP development.
• Experience in scripting languages such as Perl/Tcl/Python.

Skills

• Strong technical problem-solving and debugging capabilities.
• Ability to work independently and manage customer relationships effectively.
• Excellent communication skills for technical training and customer support.
• Willingness to travel to customer sites as required.

Benefits

• Opportunity to work with cutting-edge memory technologies for aerospace, defense, and government applications.
• Direct customer engagement and technical leadership in advanced memory design.
• Access to Intel's most advanced foundry technologies and comprehensive memory IP portfolio.
• Competitive compensation package that includes pay, stock bonuses, and benefit programs such as health, retirement, and vacation.
• Professional development in memory design methodologies and foundry services.
• Direct impact on national security through advanced memory semiconductor solutions.

Pay

Annual Salary Range for jobs which could be performed in the US: $122,440.00 - $232,190.00 USD. The range displayed reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Schedule

This role follows Shift 1 (United States of America) and is eligible for Intel's hybrid work model, allowing employees to split their time between working on-site at their assigned Intel site and off-site.