Interconnect Design Engineer
About SiFive
The pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by enabling leading technology companies to innovate, optimize, and deliver advanced solutions across various markets. SiFive’s compute platforms are pushing the boundaries of what’s possible with RISC-V, from AI and machine learning to automotive, data centers, mobile, and consumer electronics.
Job Description
The Role: SiFive seeks a senior staff level hardware engineer to design and implement enhanced TileLink interconnects, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel. The challenge involves mastering the art of designing hardware as configurable generators in a domain-specific software language, ensuring high performance and efficiency in multi-core and multi-system coherence designs.
Architect, design, and implement an enhanced TileLink interconnect, cache controllers, protocol bridges, and other infrastructure/uncore logic as RTL generators in Chisel.
Implement RTL generators such that elements self-configure to optimally connect to each other.
Enhance future designs to provide higher performance, more efficient multi-core and multi-system coherence.
Provide extensive configurability as a first-class consideration.
Integrate new design content into SiFive’s Chisel/FIRRTL framework and contribute to improvements to that framework.
Perform initial sandbox verification and work with the design verification team to create and execute thorough verification test plans.
Ensure that knowledge is shared via creation and maintenance of great documentation and participation in a culture of collaborative design.
What You Bring To The Challenge
Knowledge of cache and cache coherency architectures and concepts.
Experience with NoC or other interconnect fabrics.
Familiarity with industry-standard bus protocols (AXI, AHB, APB, CHI).
Strong software engineering skills, including:
- Object-oriented, aspect-oriented, and particularly functional programming.
- Templated metaprogramming, in any language.
- Compiler infrastructures, particularly for domain-specific languages.
- Data modeling, particularly intermediate representations for optimizing or transforming compiler passes.
- Test-driven development, particularly ability to write adaptive unit tests.
Proficiency with hardware (RTL) design in Verilog, System Verilog, or VHDL.
Attention to detail and a focus on high-quality design.
Ability to work well with others and a belief that engineering is a team sport.
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, or equivalent experience.
Nice to Have
Experience with Scala/Chisel, Bluespec, or other language/DSL for expressing configurable hardware via software.
Knowledge of RISC-V architecture.
Experience with Git/Github, Jira, Confluence.
Pay & Benefits
Consistent with SiFive values and applicable law, we provide a market-based pay structure which varies by location. The base pay range is $205,740.00 - $251,460.00. In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity. The company offers a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more!
Additional Information
This position requires a successful background and reference checks and satisfactory proof of your right to work in the United States of America. As an E-Verify employer, we use this system to confirm the employment eligibility of all new hires in accordance with federal law. All applicants will be required to complete a Form I-9, Employment Eligibility Verification, upon hire. We do not use E-Verify to pre-screen job candidates and will comply with all E-Verify regulations. California residents: please see our job candidate notice for more information on how we handle your personal information and your privacy rights: Privacy Policy Document.