Full Chip Timing Modeling and Integration Engineer
About the role
Altera is seeking highly qualified candidates to join our Full Chip Timing team. Altera continues to deliver industry-leading Field-Programmable Gate Array (FPGA) solutions to customers. As a Full Chip Timing Modeling and Integration Engineer, you will develop timing methodologies and execute full-chip timing for Altera’s next-generation product lines using the world's most advanced process technologies. This is a fast-paced, dynamic environment where you will be part of a high-performance design team working toward next-generation FPGA products. You will work hands-on performing full-chip timing analysis, leveraging your extensive design experience and interpersonal skills to solve technical issues, drive continuous improvement, and clearly communicate technical trade-offs with diverse, cross-functional, and multi-site teams. You will collaborate with cross-functional teams to define timing modeling strategies and solutions, generate high-level timing models, and integrate and validate timing models. Success in this role requires the ability to work effectively both independently and as part of a team while meeting aggressive schedules.
Responsibilities
- Develop timing methodologies and execute full-chip timing for next-generation FPGA products using advanced process technologies.
- Collaborate with cross-functional teams to define timing modeling strategies and solutions.
- Generate high-level timing models and perform timing model integration and validation.
- Perform hands-on full-chip timing analysis, including clocking and timing constraint development.
- Work with Front-End and Back-End design teams to understand