ASIC Synthesis and Timing Engineer

About the role

We are looking for an ASIC Synthesis and Timing Engineer to work on implementation of complex SoCs for next-generation satellite and space systems. You will develop the timing constraints and validate them—from RTL handoff to synthesis—and collaborate closely with architecture, RTL design, DFT, and physical design teams. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space.

In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.

Responsibilities

• Work on the RTL-to-Synthesis flow: perform synthesis at block and top level, and work with the physical design team to integrate floorplan information for physical synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).
• Collaborate with front-end engineers to assure timing closure and efficient design iteration.
• Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.
• Own Lint, CDC, and UPF checks and drive collaboration to close out issues.
• Develop an end-to-end formal verification methodology to ensure full confidence in functionality between the RTL and the post-layout netlist.
• Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.

Requirements

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 2+ years of experience in ASIC design for high-performance blocks of SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with Synthesis and constraints development.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore/outsourced PD teams or vendors.
• Able to resolve formal verification issues and analyze and fix VCLP issues regarding UPF.
• Experience with Logic equivalence check debug, Functional ECO development and implementation with minimal database disruption, and Low power checker to validate UPF.
• Familiarity with DFT integration and STA sign-off with functional ECO implementation.
• Excellent communication, leadership, and cross-functional collaboration skills.

Nice to Have

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Comprehensive benefits package including paid time off, medical/dental/vision coverage, life insurance, and paid parental leave.
• Many other perks.

Pay

Base salary range for this role is $130,000 – $200,000 + equity in the company. Salary will be based on several factors including, but not limited to: knowledge and skills, education, and experience level.