Distinguished Silicon Architect

Key Responsibilities

• Engage with customers to understand their pain points
• Encode chip-design expertise (RTL/DV best practices, microarchitectural patterns, failure modes) into reusable, agent-consumable knowledge and playbooks
• Define EDA tool usage for agents—when to run simulation, lint, CDC, synthesis, and STA, how to interpret results, and how to chain tools into reliable flows
• Design end-to-end agent workflows for chip design, verification, debugging, and iterative refinement using structured process graphs
• Decompose complex silicon workflows into executable agent steps with clear inputs, outputs, and success criteria, including hierarchical and iterative patterns
• Develop high-quality prompts covering specification, microarchitecture, RTL, verification, and debug
• Define agent behavior models, guardrails, and few-shot examples that guide reasoning, assumption validation, and error handling in chip-design tasks

Required Qualifications

• 20+ years of experience (Staff) across the key domains: Chip Design & Verification, Digital IC, ASIC, or SoC design or verification, with strong hands-on expertise in SystemVerilog RTL and UVM
• Deep familiarity with lint, CDC/RDC, simulation, timing constraints, and STA, and a solid understanding of microarchitecture (pipelines, FIFOs, DMA, caches, interconnects)
• Ability to clearly explain design tradeoffs and debugging strategies
• Agenic AI & Software Experience with LLM-based agent systems, prompt engineering, and workflow decomposition
• Familiarity with agent orchestration frameworks such as LangGraph, LangChain, AutoGen, or CrewAI, or equivalent custom systems
• Proficiency in Python and experience integrating external tools into automated workflows