Digital Verification Engineer - New Grad

Technical Experience and Personal Skills Required

• Graduated/graduating in 2026 from Electrical or computer engineering, computer science or other applicable scientific degree at the BEng/BSc or MEng/MSc level
• A highly motivated self-starter, able to work independently, while being a team player
• Ability to methodically solve complex technical problems
• Excellent organization, written and oral (English) communication skills
• Proficiency above the intermediate level with the use of System Verilog, SVA, and simulators from major vendors
• Proven ability in determining appropriate and comprehensive digital verification and coverage strategies

Responsibilities

• Implement innovative verification strategies to thoroughly simulate and validate functional blocks and subsystems for the Wavelogic family of products
• Read and understand the functional requirements specification document(s)
• Communicate and collaborate with systems engineers and architects
• Create the verification, functional coverage and formal verification test plans
• Participate in the creation of testbench environment and/or components, agents, scoreboard, and all test scenarios related to your architectural functional block using System Verilog UVM and/or C where applicable
• Perform coverage driven verification, monitor regressions and debug resulting failures with the help of the function's designer
• Report on status updates on a regular basis

Qualifications

The Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions, and are one of the main contributors to Ciena's success in the telecommunications industry.

Benefits

• Comprehensive benefits package including medical, dental, and vision plans
• Company-paid holidays
• Paid sick leave
• Paid vacation time

Schedule

Not specified

Pay

• The annual pay range for this position is $79,300 - $126,700