DFT Tech Lead

About The Position

We are looking for a talented and experienced DFT Tech Lead.

Responsibilities

• Create SoC DFT strategy and architecture (ATPG/DFT/MBIST)
• Work on hierarchical design
• Debug all Design Rule checks, apply design fixes to achieve high test quality
• Insert all DFT logic - boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Insert and hook up MBIST logic.
• Define test plan for special analog IPs and implement.
• Document DFT architecture and test sequences, including boot-up sequence associated with test pins.

Requirements

• Minimum qualifications:
• - 8+ Experience in DFT specification definition, architecture, insertion, and analysis in designs
• - Experience in silicon bring-up, debug, and validation of DFT features on ATE, debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG-related issues
• - Experience in fault modeling
• Preferred qualifications:
• - Master's degree in Electrical Engineering.
• - Experience in IP integration (memories, Test controllers, TAP, MBIST).
• - Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
• - Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
• - Excellent attention to detail organizational, problem-solving, and communication skills.