DFT Engineers

About the role

We are looking for experienced DFT Engineers to join our semiconductor engineering team. The ideal candidates will have strong hands-on experience in Design for Test (DFT), ATPG, and SoC/ASIC testing.

Location: Santa Clara, CA

Responsibilities

• Develop and support DFT architectures for SoC and ASIC designs.
• Generate, analyze, and debug ATPG test patterns.
• Implement and validate scan-based testing methodologies.
• Work on MBIST architectures, memory testing, and diagnostics.
• Support IO Test methodologies for interface and pin-level validation.
• Perform clock DFT implementation and verification.
• Review RTL and digital design fundamentals related to DFT.
• Use industry-standard DFT and ATPG EDA tools.
• Troubleshoot complex test issues and support high-performance semiconductor programs.
• Collaborate with design, verification, and test teams to meet project requirements.

Requirements

• 5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs.
• Strong understanding of DFT fundamentals, including controllability, observability, and scan testing.
• Proven experience in ATPG pattern generation, analysis, and debug.
• Hands-on experience with MBIST, memory test architectures, and diagnostics.
• Knowledge of IO Test methodologies and pin-level validation.
• Understanding of clock DFT and clock verification concepts.
• Strong knowledge of digital design and RTL fundamentals.
• Experience with industry-standard DFT/ATPG EDA tools.
• Strong analytical, problem-solving, and communication skills.
• Ability to work in a fast-paced semiconductor engineering environment.

Skills

• Experience with advanced SoC/ASIC designs.
• Experience debugging complex DFT and ATPG issues.
• Ability to collaborate with cross-functional engineering teams.