DFT Design Engineer

About the role

We are looking for an SoC/ASIC Digital Design Engineer with expertise in Design for Test (DFT). This role requires intimate knowledge and hands-on experience in scan chain insertion, compression scan technologies, memory built-in self-test (MBIST), and automatic test pattern generation (ATPG). Candidates should follow systematic, quality-metrics-driven ATPG pattern generation and possess strong skills in synthesis, verification, and debugging Verilog testbenches.

Responsibilities

• Perform DFT insertion flows, including basic scan chain insertion using synthesis or other software tools.
• Implement compression scan insertion, logic built-in self-test (LBIST), and other scan technologies.
• Develop and apply memory built-in self-test (MBIST) methodologies.
• Generate ATPG patterns to achieve design test coverage goals, ensuring systematic quality metrics.
• Debug and analyze failures to improve fault coverage.
• Verify ATPG testbenches and debug root causes of simulation mis-compares.
• Work with JTAG (1149.1/6), IEEE1500, and IEEE1687 standards.
• Collaborate with cross-functional teams, including architecture, design, and internal/external customers.
• Complete DFT tasks independently while maintaining a disciplined, thorough, and methodical approach.

Requirements

• 3–12 years of professional experience in SoC/ASIC Digital Design with a focus on DFT.
• Intimate knowledge of DFT insertion flows and scan technologies.
• Hands-on experience with compression scan insertion, LBIST, and MBIST.
• Expertise in ATPG to achieve design test coverage goals.
• Working knowledge of JTAG (1149.1/6), IEEE1500, and IEEE1687.
• Strong problem-solving skills and ability to work in a collaborative team environment.
• Self-driven, committed, and capable of working in a fast-paced project environment.
• US citizenship preferred.

Qualifications

• Prior experience with Cadence tools and flows is highly desirable.
• Knowledge of timing analysis and equivalency checks is a plus.
• Strong debugging skills for Verilog testbenches and ATPG simulations.