DFT Engineer

About the role

We are seeking a motivated Design for Test (DFT) Engineer to join our team. This is an ideal role for someone with a solid grasp of digital logic and a passion for hardware reliability. You will support the end-to-end DFT flow, from RTL integration to ATPG pattern generation, while learning to navigate the complexities of massive-scale chip design.

Responsibilities

• RSA: Assist in integrating DFT features such as scan compression, memory BIST, IEEE 1149, IEEE 1687, and IEEE 1500 wrappers into the design.
• Scan & ATPG: Execute scan insertion scripts and run ATPG (Automatic Test Pattern Generation) for various fault models, including stuck-at and transition faults.
• Simulation & Debug: Run and debug gate-level simulations (GLS) to verify DFT structures and investigate simulation mismatches.
• Coverage Analysis: Help identify areas of low test coverage and work with senior engineers to implement logic changes or test points to improve results.
• Verification: Support the validation of test patterns for low-power designs and assist in timing constraint verification for scan modes.
• Automation: Maintain and improve Tcl, Perl, or Python scripts to streamline the DFT flow and post-processing of design data.

Requirements

• Experience: 3-5 years of experience in DFT or Digital Design (relevant internships or university projects count!)
• Education: A Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• Core Knowledge: A strong understanding of digital logic design, Verilog/SystemVerilog, and basic DFT concepts (Scan, ATPG, BIST).
• Scripting Skills: Familiarity with Tcl, Python, or Perl for workflow automation
• Tool Exposure: Basic experience or academic exposure to industry-standard tools (e.g., Cadence Modus/Genus, Synopsys Tessent/DFTMAX, or Siemens Fastscan).

Qualifications

• Mindset: A "can-do" attitude, a desire to learn complex hierarchies, and excellent communication skills for cross-functional collaboration.
• Bonus Points: Knowledge of RISC-V architecture or CPU fundamentals.
• Experience with Gate Level Simulations (GLS) and timing analysis.
• Exposure to hardware description languages like VHDL or specialized DFT protocols like IJTAG (IEEE 1687).
• Knowledge or experience using ATE test systems (Advantest 93K, Teradyne Ultra-Flex, etc).