DFM RET Engineer

Responsibilities

• Develop, evaluate, and implement advanced OPC models and recipes for 28nm and equivalent advanced node technologies
• Perform comprehensive DFM analysis on product designs, identifying and mitigating potential manufacturing issues (e.g., hotspots, yield detractors)
• Collaborate with design teams to define DFM guidelines and ensure layout compliance with manufacturing capabilities
• Work with lithography and process engineering teams to optimize OPC recipes and improve patterning performance, yield, and process window
• Interface with OPC and lithography engineers to co-optimize layout structures for printability
• Analyze lithography process data and wafer yield data to identify root causes of patterning defects and drive corrective actions
• Evaluate and qualify new OPC/DFM software tools and methodologies
• Develop and maintain automation scripts for OPC/DFM flows
• Contribute to DFM-aware layout methodologies for custom analog IPs
• Mentor junior engineers and contribute to team knowledge sharing

Qualifications

• Minimum Requirements: Master’s or Ph.D. in Electrical Engineering, Physics, Materials Science, or related field, 5+ years of hands-on OPC and DFM experience in the semiconductor industry, Strong understanding of optical lithography principles and RET (OPC, SRA, assist features, mask technology), Hands-on experience with industry-standard OPC tools (e.g., Synopsys Sentaurus Lithography, Siemens EDA Calibre, ASML Brion), Familiarity with 28nm/22nm process constraints and lithographic limitations, Proficiency in scripting languages (Python, TCL, Perl, or equivalent)
• Preferred Qualifications: Experience with analog layout interaction with lithography and OPC flows, Familiarity with layout tools (e.g., Cadence Virtuoso); knowledge of DRC and LVS, Experience applying machine learning or AI techniques to OPC/DFM problems, Strong cross-functional collaboration and analytical skills