Design Verification Engineer

Overview

Microsoft is a highly innovative company that collaborates across disciplines to produce cutting‑edge technology that changes our world. Microsoft’s Silicon team builds custom silicon for a diverse set of systems ranging from innovative consumer products like Xbox to high‑performance Azure cloud servers, clients, and augmented reality.

Responsibilities

• Plan the verification of complex design IP/SoC, interacting with architecture and design engineers to identify verification test scenarios.
• Create and enhance constrained‑random verification environments using SystemVerilog and UVM, or formally verify designs with SVA and industry‑leading formal tools.
• Develop tests using UVM or C/C++.
• Analyse and debug test failures with designers to deliver functionally correct design.
• Identify and write functional coverage for stimulus and corner cases.
• Close coverage gaps to plug verification holes and meet tape‑out requirements.

Qualifications

• 3 or more years of experience in design verification with a proven track record of delivering complex CPU or SoC IPs.
• Knowledge of verification principles, testbenches, stimulus generation, and UVM or C++‑based test environments.
• Good understanding of computer architecture.
• Substantial background in debugging RTL (Verilog) designs as well as simulation and/or emulation environments.
• Proficiency with scripting languages such as Python or Perl.