Design Verification Engineer

Key Responsibilities

• Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
• Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
• Debug complex datapath and protocol issues in RTL and testbench environments.
• Work closely with architects and designers to validate functionality and design intent.
• Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
• Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

Requirements

• Proficiency with UVM and System Verilog.
• Strong debugging and problem-solving skills for complex digital designs.
• Solid knowledge of computer architecture and digital design fundamentals.
• Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.
• Strong candidates may also have experience with:
• Familiarity with System Verilog Assertions (SVA) and formal verification techniques.
• Experience verifying systolic arrays, DMA engines, or NoC/AXI protocols.
• Scripting skills (Python/Perl/TCL or similar) for automation, debug, and regression flows.