Design Verification Engineer

About the role

Develop and execute block-level and subsystem-level verification plans for complex FPGA and SoC designs.
Create reusable SystemVerilog and UVM-based verification environments, agents, sequences, scoreboards, and checkers.
Create and maintain assertions using SystemVerilog Assertions (SVA) to improve design quality and identify functional issues early.
Debug simulation failures, functional bugs, and RTL issues by working closely with RTL designers, architects, and firmware engineers.
Perform coverage analysis including functional, code, toggle, and assertion coverage to ensure verification completeness.
Develop verification infrastructure, automation, and regression environments to improve engineering productivity.
Participate in design reviews, verification reviews, and bug triage meetings throughout the development lifecycle.
Collaborate with emulation, FPGA prototyping, post-silicon validation, and software teams to support product bring-up and validation.

Qualifications

• Bachelor's Degree In Electrical Engineering, Computer Engineering, Computer Science, Or a Related Technical Discipline With 4+ Years Of Industry Experience In Digital Design Verification, ASIC Verification, FPGA Verification, Or SoC Verification, Including The Following 4+ years of experience verifying digital ASIC, FPGA, or SoC designs using SystemVerilog and Universal Verification Methodology (UVM).
• 4+ years of experience developing constrained-random and directed verification testbenches for complex digital designs.
• 3+ years of experience writing SystemVerilog Assertions (SVA) and applying assertion-based verification methodologies.
• 3+ years of experience using industry-standard simulation tools such as Synopsys VCS, Cadence Xcelium, Siemens QuestaSim, or equivalent simulators.
• 3+ years of experience debugging RTL functional issues using waveform analysis, simulation debugging tools, and verification methodologies.
• 3+ years of experience developing verification components including UVM agents, drivers, monitors, scoreboards, sequences, and functional coverage models.
• 3+ years of experience analyzing functional coverage, code coverage, assertion coverage, and coverage closure metrics.
• 2+ years of experience using scripting languages such as Python, Perl, Tcl, Shell, or similar languages to automate verification workflows and regression environments.
• 2+ years of experience using revision control systems such as Git, Perforce, or equivalent version control tools.
• 2+ years of experience collaborating with RTL design, architecture, physical design, firmware, or software engineering teams throughout the product development lifecycle.
• 1+ year of experience developing automated regression environments and analyzing regression results to improve verification quality and productivity.
• 1+ year of experience verifying one or more high-speed digital interfaces such as PCIe, Ethernet, DDR, LPDDR, HBM, AXI, AMBA, USB, CXL, or similar industry-standard protocols.