Jobs · North Carolina

Design Verification Engineer

Microsoft · Raleigh, NC · 6 days ago
Hybrid$102k–$202k/yrFull-time

Responsibilities

  • Own or lead verification of components used in Fabric Interconnect
  • Learn about the design and interact with partner teams to define verification strategies and test plans
  • Develop UVM-based or Formal verification environments and run and debug simulations to drive quality
  • Apply random-stimulus and coverage-based techniques to find bugs and meet test plan goals
  • Innovate to improve verification efficiency through methodologies or tools
  • Apply industry leading generative AI solutions to verification work
  • Coach and mentor others in your areas of expertise
  • Demonstrate Microsoft core values: Customer Focus, Adaptability, Collaboration, Growth Mindset, Drive for Results, Influence for Impact, Judgement, and Diversity & Inclusion

Qualifications

  • Required Qualifications: Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 1+ year(s) technical engineering experience OR Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 2+ years technical engineering experience OR equivalent experience.
  • Screening Requirements: Ability to meet Microsoft, customer and/or government security screening requirements are required for this role.
  • Preferred Qualifications: 1+ years of pre-silicon subsystem or IP verification experience. Demonstrated experience in verification of designs that utilize Coherent Hub Interface (CHI) and Advanced Microcontroller Bus Architecture (AMBA) protocols. Demonstrated understanding in one or more of the following: fabric interconnects, coherency, virtualization, security, interrupts, PCIe, CXL, and/or protocol bridges. Experience with writing IP/block or subsystem level test plans, developing tests, debugging failures and coverage signoff. Experience creating, maintaining, or integrating test benches, checkers and stimulus using Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), and optionally Python based post-processing checking. Aptitude for writing scripts/software with industry standard languages like Python. Experience applying generative AI to day-to-day tasks.

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