DDR Memory Interface System Validation Lead Engineer

About the role

We are seeking a highly motivated and experienced DDR5 / LPDDR5 Memory Validation Engineer to join our Silicon and Platform Validation organization.

Responsibilities

• Own DDR5 and LPDDR5 memory subsystem validation, including defining and executing validation strategies across multiple FPGA programs.
• Create, define, and develop comprehensive system-level validation environments and test suites for advanced memory interface validation.
• Perform pre-silicon and post-silicon functional and electrical validation of DDR5 and LPDDR5 controllers, PHYs, and associated high-speed interfaces.
• Develop and execute validation plans covering:
  • Memory initialization and training
  • Read/write functional validation
  • System margining and stress testing
  • Frequency scaling
  • Memory controller features validation
  • Stability and reliability validation
  • Error injection and recovery testing
• Analyze signal integrity and timing behavior for high-speed memory interfaces, including eye diagrams, jitter, and timing margins.
• Debug complex silicon, firmware, board-level, and system-level issues involving memory subsystems and PHY behavior.
• Collaborate with hardware board design teams on high-speed memory channel implementation, including:
• Stack-up reviews
• Routing strategies
• SI/PI considerations
• Memory topology optimization
• Termination and power delivery schemes
• Review schematics, layouts, and board design guidelines for DDR5 and LPDDR5 implementations.
• Utilize industry-standard protocol analyzers, oscilloscopes, logic analyzers, and traffic generators for debug and characterization.
• Develop, standardize, and maintain validation methodologies, automation frameworks, and measurement flows to improve validation scalability and efficiency.
• Partner with silicon design, package, board, firmware, and software teams to drive root-cause analysis and issue resolution.
• Collaborate with pre-silicon validation teams to improve post-silicon coverage and future debug capabilities.
• Drive innovation in validation infrastructure, automation, and platform enablement to improve throughput and test coverage.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.
• Minimum of 8+ years of industry experience in memory subsystem validation, silicon validation, or high-speed interface validation.

Benefits

Salary Range: $149,100 - $215,000 USD

We also offer incentive opportunities that reward employees based on individual and company performance.