Principal DDR5 / LPDDR5 PHY Validation Engineer

About The Role

Own DDR5 / LPDDR5 PHY-focused validation strategy across bring-up, tuning, and release readiness.
Lead DDR5 / LPDDR5 training/tuning validation and optimization (read/write leveling, timing alignment, Vref, ODT/termination, training convergence).
Drive signal-quality analysis and root-cause using eye/margin/jitter/clocking and correlation to BER/error rate.
Build and extend DDR5 / LPDDR5 validation automation and debug tooling using C for execution, logging, sweeps, and data reduction.
Provide principal-level technical leadership through complex debug ownership, engineering mentoring, and evidence-based reporting/recommendations.

About You

• 6+ years of DDR5 / LPDDR5 PHY expertise in bring-up validation, training/tuning, and stability issue resolution.
• Solid background in DDR5 / LPDDR5 Compliance testing.
• Strong oscilloscope-based debug skills using eye, jitter, clock, and data observations.
• Deep knowledge of how SI/PI impacts DDR5 / LPDDR5 behavior and link stability.
• C Competence in analog characterization and turning measurements into clear go/no-go performance decisions.
• Python proficiency to build automation and debug tools for validation flows.
• Additional skills highly desired: JEDEC Education BS degree in Electrical Engineering, Computer Engineering, or Computer Science & 8 years of related experience; MS degree & 6 years