Custom Analog Design Automation Lead

About the role

Position Summary: Altera is seeking a Custom-Analog Design-Automation Lead to drive analog design automation and engineering productivity across the custom-analog design organization, with a strong emphasis on AI-assisted design flows. This role owns the strategy and execution for automating analog design tasks, embedding AI/ML-driven methodologies into the design cycle, and scaling productivity gains across multiple design teams.

Role Purpose: Lead analog design automation and productivity initiatives, including the development and deployment of AI-assisted design flows, to accelerate cycle time, improve quality of results, and reduce manual effort across custom-analog design programs.

Job Type: Regular. Shift: Shift 1 (United States of America). Primary Location: San Jose, California, United States. Applicants must be eligible for any required U.S. export authorizations. We use artificial intelligence to screen, assess, or select applicants for the position.

Responsibilities

• Define and drive the technical strategy and roadmap for analog design automation and AI-assisted productivity tools.
• Develop, deploy, and maintain automation flows that span custom-analog design tasks, from schematic and layout through verification and signoff.
• Identify opportunities to apply AI/ML techniques to analog design problems (e.g., sizing, layout assistance, verification triage) and lead proof-of-concept through production deployment.
• Own the reuse and hardening strategy for analog IP and automation flows, ensuring methodologies are robust, well-documented, and portable across projects.
• Partner with design, CAD, and methodology teams to roll out automation and AI-assisted capabilities consistently across fabric, SerDes, and IO design groups.
• Establish metrics to track productivity, quality, and adoption of automation and AI-assisted flows, and report progress to engineering leadership.
• Mentor and provide technical direction to design and automation engineers adopting new flows and methodologies.
• Stay current with emerging EDA, automation, and AI/ML technologies relevant to custom-analog design, and evaluate them for adoption.
• Scope: Analog design automation spanning fabric, SerDes, and IO design domains; reuse and hardening strategy for analog design IP, flows, and methodologies; cross-team methodology deployment, influencing practices across multiple design groups rather than a single project.

Qualifications

Minimum Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
• 12+ years of experience in custom-analog circuit design and/or analog design automation, combined with hands-on experience in design automation and/or AI-assisted methodologies.
• Demonstrated ability to develop and deploy design automation methodology across multiple teams, not just within a single project.
• Working knowledge of analog/mixed-signal design flows (schematic capture, layout, extraction, verification) and the EDA toolchains that support them — Cadence Virtuoso Studio, Maestro/ADE, Spectre, Quantus QRC, Voltus-XFi/EMIR, Synopsys HSPICE/PrimeSim, or equivalent.
• Expert-level scripting and automation ability (Cadence SKILL, Python, Tcl, shell), sufficient to build and maintain production automation rather than extend what already exists.
• Demonstrated application of AI/ML to design or verification workflows, taken past proof-of-concept into production use by engineers other than the author.
• Direct experience working with foundry PDKs and EDA vendors to debug, characterize, and qualify tool behaviour at advanced nodes (e.g., Intel 18A / TSMC N3 / N5) and comparable.
• Strong communication and leadership skills, with the ability to influence design practices across fabric, SerDes, and IO teams.

Preferred Qualifications

• Prior experience leading a Center of Excellence (CoE) or cross-functional capability team.
• Experience with machine-learning-assisted EDA tools or building custom AI/ML tooling for circuit design tasks.
• Track record of IP reuse and hardening strategies that reduced design cycle time across multiple tapeouts.

Pay

$231,500 - $341,075 USD (Bay Area California only; actual