CPU Architecture Verification Engineer

About the role

Nuvacore is building a high‑performance, low‑power CPU for next‑generation compute workloads. As a Verification Engineer on the design‑verification team, you will drive architectural verification of the CPU, building stimulus, checkers, and flows that find architectural bugs before silicon, working closely with architecture and RTL design.

Responsibilities

• Plan & Strategy: Drive the verification scope, strategy, and test plans for architectural correctness — the CPU's behavior and architectural state versus the specification and a golden reference model.
• Environment Setup: Build, maintain, and scale robust verification environments — including co‑simulation against the golden reference model — that compare architectural state end to end.
• Test & Debug: Generate stimulus in assembly and random instruction sequences (RIS) to exercise the full instruction set and architectural corner cases such as exceptions, interrupts, and privilege transitions.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the architectural test plan is complete.
• Cross‑functional Collaboration: Partner with architects and RTL teams to root‑cause mismatches across RTL, model, and specification, drive design fixes, and support emulation, FPGA, and silicon bring‑up.

Requirements

Must Have

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design‑verification experience, ideally on a CPU or complex digital design.
• Strong knowledge of CPU architecture and micro‑architecture — instruction set, architectural state, exceptions, and privilege model — with a good understanding of at least one modern ISA (x86, ARM, or RISC‑V).
• Hands‑on functional verification: test plans, testbenches, checkers, and coverage.
• Proficiency in C/C++/Rust and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests in assembly for CPU verification.

Nice To Have

• Architectural / instruction‑set verification against a golden reference model.
• Random instruction sequence (RIS) stimulus generation.
• Exceptions, interrupts, privilege levels, and virtualization.
• Constrained‑random verification and coverage‑driven closure.
• Assertions and formal verification.
• Emulation/FPGA and silicon bring‑up and debug (waveforms, trace).