CPU Verification Engineer

About the role

• Plan & Strategy: Drive the verification scope, strategy, and test plans for the CPU at unit and/or top level of the CPU design.
• Environment Setup: Build, maintain, and scale robust verification environments — stimulus generators, checkers, transactors, and coverage — that exercise the pipeline end to end.
• Test & Debug: Generate complex directed and random tests in assembly, C, or random instruction sequences (RIS) to expose corner cases such as speculation, hazards, flushes, and retirement ordering.
• Performance Verification: Partner with architects to correlate RTL against performance models, hunting throughput, stall, and branch-prediction-accuracy issues.
• Coverage Closure: Define the coverage space, write functional coverage monitors, and analyze metrics to prove the test plan is complete.
• Cross-functional Collaboration: Partner with architecture and RTL teams to root-cause failures, drive design fixes, and support emulation, FPGA, and silicon bring-up.

Requirements

Must Have

• Degree in Electrical/Computer Engineering, Computer Science, or equivalent practical experience.
• 15+ years (Principal) or 4+ years (Senior Engineer) of design-verification experience, ideally on a CPU or complex digital design.
• Strong knowledge of CPU micro-architecture and digital logic — pipelines, out-of-order execution, and branch prediction.
• Hands-on functional verification: test plans, testbenches, checkers, transactors, and coverage.
• Proficiency in C/C++ and/or SystemVerilog, plus a scripting language (Python; Perl a plus).
• Experience writing and debugging tests in assembly for CPU verification.

Nice To Have

• Experience on one or more of Front-end / execution-unit verification, load/store cache verification, SoC/System verification, Debug/Power mgmt verification.
• Random instruction sequence (RIS) stimulus generation.
• Constrained-random verification and coverage-driven closure.
• Assertions and formal verification.
• Emulation/FPGA and silicon bring-up and debug (waveforms, trace).
• Driving a verification problem end-to-end to sign-off.