Jobs · Information Technology · California

Core Performance Architect

SiFive · Santa Clara, CA · 3 wk ago
HybridInformation Technology$159k–$194k/yrFull-time

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. Our unrivaled compute platforms enable leading technology companies to innovate, optimize, and deliver advanced solutions across markets such as artificial intelligence, machine learning, automotive, data center, mobile, and consumer.

About the role

SiFive, a leader in RISC-V CPU IPs, is looking for an experienced leader to research and develop next-generation high-performance processors. The performance architect will guide the performance team to collaborate closely with architects and design teams to develop the highest performance core architecture and micro-architecture.

Responsibilities

  • Work with a team of performance engineers to research, model, and develop architecture/micro-architecture ideas for state-of-the-art performance processors that meet aggressive performance targets.
  • Design and carry out experiments to research and develop architecture/micro-architecture features.
  • Collaborate with the design team to implement and deliver performance targets in RTL.

Requirements

  • MS in Computer Science or Computer Architecture.
  • 1+ years of experience in high-performance processor development.
  • 1+ years of involvement in engineering teams to deliver hardware or software products.
  • Hands-on expertise with hardware development (RTL/implementation flows, verification/validation, backend flows, FPGA flows) or FPGA debug, including the use of Integrated Logic Analyzer for waveform capture and debug.
  • Knowledge in analyzing performance bottlenecks in micro-architecture and software stack. Awareness of potential security vulnerabilities is a plus.
  • Strong foundation in computer architecture of high-performance out-of-order CPU designs. Familiarity with known industry micro-architectures is a plus.
  • Strong foundation in workload characterization to identify hardware/software performance bottlenecks.
  • Strong foundation in workload reduction techniques for efficient performance simulation and projection.

Pay

We have a market-based pay structure which varies by location. The base pay range is a guideline reflecting the cost of labor in the U.S. geographic market based on the role's location. Pay within these ranges varies depending on job-related knowledge, skills, and relevant work experience. For candidates who receive an offer, the starting salary will vary based on qualifications, skill level, competencies, and work location.

Base Pay Range: $158,760.00–$194,040.00

In addition to base pay, this role may be eligible for variable/incentive compensation and/or equity.

Benefits

This role is eligible for a comprehensive, competitive benefits package which may include healthcare and retirement plans, paid time off, and more.

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