ASIC/FPGA Design and Verification Engineer - (Lead, Senior, or Principal)
Boeing · Albuquerque, NM · 6 days ago
Engineering$137k–$185k/yrFull-time
About the role
Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for multiple ASIC/FPGA Design or Verification Engineers (Lead, Senior, or Principal) to join us as part of our Boeing Electronic Products team at the heart of Boeing’s products; ASICs and FPGAs in Albuquerque, NM.
Responsibilities
- Conduct unit-level testing, verification, and validation of embedded software and firmware, utilizing debugging tools like oscilloscopes and logic analyzers to identify and resolve issues.
- Create and maintain technical documentation, including requirements documents, design specifications, test plans, and interface control documents.
- Support the integration of software and hardware components, from initial hardware bring-up to final system validation.
- Analyze and enhance the efficiency, stability, scalability, and performance of system resources, often within the constraints of low power or memory.
Requirements
- Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement.
- 9+ years of ASIC/FPGA design or verification experience (or minimum Master’s and 7+ years of ASIC/FPGA design or verification experience).
Qualifications
- Experience with ASIC/FPGA architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs.
- Professional experience with hardware-based integration and test of ASIC/FPGA designs.
Skills
- Experience with hardware emulators, especially Palladium.
- Proficiency with hardware verification languages: System Verilog, System Verilog Assertions.
- Ability to execute test plans.
- Proficiency with Object Oriented Programming Concepts: Inheritance, Polymorphism, etc.
- Experience developing Functional Coverage Models and Closing Code Coverage.
- Experience with high-speed Serdes interfaces (JESD204C, PCIe, Ethernet).
- Proficient in scripting languages: Make, Perl, Python, etc.
- Revised Control Systems: svn, cvs, git.
- Proficient in Linux Environments.
- Familiarity with space-based design techniques and radiation mitigation.
Benefits
This position requires the ability to obtain a US Security Clearance for which the US Government requires US Citizenship as a condition of employment. An interim and/or final U.S. Secret Clearance Post-Start is required.