Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)

What You Will Do

• Verification environment architecture and design using SystemVerilog with OVM/UVM
• Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking
• Testbench development for the verification of RTL blocks using VHDL or SystemVerilog
• Contribute to engineering estimates for new program pursuits.
• Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status

Qualifications

• You Must Have:
• Typically requires a degree in Science, Technology, Engineering or Mathematics (STEM) and minimum 5 years prior relevant experience or an Advanced Degree in a related field and minimum 3 years of experience
• Active and transferable U.S. government issued security clearance is required prior to start date
• U.S. citizenship is required, as only U.S. citizens are eligible for a security clearance
• ASIC/FPGA experience with RTL coding, simulation, and verification using VHDL and/or Verilog, including development of testbenches for RTL block verification using VHDL and/or SystemVerilog
• Working knowledge of chip-level verification methodologies and tools, including constrained-random verification, functional coverage, SystemVerilog, and revision control systems such as Git or Subversion
• We Prefer:
• Ability to work independently and collaboratively in multidisciplinary engineering teams supporting fast-paced, milestone-driven programs
• Strong written and verbal communication skills
• Experience with ASIC/FPGA lab validation, DFT and manufacturability concepts, Unix/Linux environments, scripting or C/C++, and industry-standard simulation and synthesis tools such as QuestaSim, Quartus, Synplify, or Vivado

Pay

N/A

Schedule

N/A

Benefits

N/A