ASIC Design Verification Engineer

About the Role

The focus of this role is to own the verification strategy and coverage closure for AMD's mixed-signal power management IP, driving system-level verification of the full SOC while also contributing block-level verification and RTL design.

Responsibilities

• Verification Ownership & Coverage
  • Own the overall verification strategy, test plan, and coverage closure for a mixed-signal power management IC
  • Define functional and code coverage goals, track progress against them, and report verification status and readiness to the project team
  • Own verification signoff criteria and drive the team to coverage closure ahead of tape-out
  • Maintain and improve regression infrastructure, triage flow, and results reporting
• System-Level Verification
  • Develop and execute system-level verification of the full SOC, including boot and reset sequencing, power state transitions, fault and protection scenarios, and host interface traffic
  • Verify firmware-driven behavior in co-simulation of embedded firmware with RTL
  • Build and maintain SystemVerilog/UVM testbench components, sequences, checkers, and assertions at the system level
• Block-Level & Mixed-Signal Verification
  • Develop block-level test benches and coverage for digital blocks as project needs require
  • Verify digital/analog interfaces using real-number models (RNM) of analog macros, including model bring-up, correlation to analog behavior, and debug in the digital simulation environment
  • Partner with Analog Design and RTL Design to review model fidelity and ensure the verified behavior matches silicon intent
• Collaboration & Design Support
  • Partner with RTL designers on design reviews, verification planning, and debug of failures to root cause
  • Contribute to SystemVerilog RTL design work across the team as needed
  • Support post-silicon bring-up, including correlation of silicon behavior back to pre-silicon test cases
  • Work across Analog, Firmware, Systems Engineering, and Architecture teams; mentor junior engineers on verification methodology

Qualifications

• Bachelor's or master's in electrical/computer engineering
• Passion for finding bugs and thinking in terms of coverage, corner cases, and unexercised scenarios
• Comfortable reading RTL as well as writing testbenches
• Strong analytical and problem-solving ability with persistence to chase intermittent failures to root cause
• Excellent communication skills and a team-player mindset

Preferred Skills

• System-level or SOC-level verification ownership on a mixed-signal device
• Real-number modeling (RNM) of analog blocks in SystemVerilog (wreal / nettype real), or experience with Verilog-AMS
• SystemVerilog RTL design experience in an ASIC environment
• Firmware/RTL co-simulation or hardware/software co-verification experience
• Formal verification, assertion-based verification (SVA), or emulation/FPGA prototyping experience
• Post-silicon bring-up and debug experience
• Experience mentoring engineers and leading verification reviews
• Strong SystemVerilog and UVM testbench development skills, with ownership of verification for a block or subsystem through tape-out
• Demonstrated experience defining verification plans and driving functional and code coverage to closure
• Proficiency with simulation, coverage, and debug tools, and with regression automation
• Ability to read and understand RTL and design specifications to independently derive test intent

Benefits

Benefits offered are described at AMD benefits at a glance.

This role is not eligible for visa sponsorship.