ASIC Verification Engineer

Hybrid Work Arrangement

This is a hybrid role based in Durham, NC with an expectation that you will work on average two days per week from an HPE office.

About HPE

Hewlett Packard Enterprise is the global edge‑to‑cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes at the speed required to thrive in today’s complex world. Our culture thrives on finding new and better ways to accelerate what’s next, values varied backgrounds, and offers flexibility to manage work and personal needs.

Position Summary

We are seeking a highly motivated ASIC Verification Engineer to join our networking silicon development team.

Key Responsibilities

• Own and drive block‑level or subsystem verification efforts, from creating test plans to achieving comprehensive coverage closure.
• Develop, enhance, and maintain advanced UVM verification environments, including agents, sequences, scoreboards, virtual sequences, and register models.
• Perform constraint‑driven random testing, debug complex SoC designs, and ensure functional coverage and assertion goals are met.
• Analyze simulation results using industry‑leading simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and debug waveforms to validate design functionality.
• Collaborate with cross‑functional teams to identify and resolve issues, ensuring high‑quality ASIC/SoC deliverables.

Required Skills and Qualifications

• 4+ years of experience in ASIC/SoC verification with a proven track record of owning verification from test plan to coverage closure.
• Strong expertise in SystemVerilog and UVM methodology, including developing environments from scratch.
• Deep understanding of randomization, constraints, functional coverage, and assertions (SVA).
• Hands‑on experience in test planning, coverage analysis, and debugging of complex SoC designs.
• Proficiency with industry‑standard simulation tools (e.g., Cadence Xcelium, Synopsys VCS, Mentor Questa) and waveform debugging.

Preferred Skills and Experience

• Experience verifying networking ASICs or router datapath/control blocks, such as packet processing, forwarding engines, or fabric interfaces.
• Familiarity with high‑speed interconnects, buffers, or scheduling pipelines in large networking SoCs.
• Exposure to emulation environments, hardware acceleration, or traffic‑model integration.
• Knowledge of coverage analytics, regression dashboards, and continuous‑integration flows (e.g., Jenkins).
• Understanding of low‑power (UPF) or formal verification methodologies.
• Experience with post‑silicon bring‑up and debug is a plus.
• Familiarity with emulation environments and debug flows is desirable.

Accessibility

HPE is committed to creating an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you require accommodation during any stage of the application or interview process, please submit your request through our secure accommodation form.

What We Can Offer You

• Health & Wellbeing: Comprehensive benefits supporting physical, financial, and emotional wellbeing for you and your loved ones.
• Personal & Professional Development: Programs to help you reach career goals, become a knowledge expert, or apply your skills across divisions.
• Unconditional Inclusion: An inclusive environment that celebrates individual uniqueness and offers flexibility to manage work and personal needs.

Pay

Annual salary range for this position in North Carolina is USD 105,500 – 243,000 (base salary). Variable incentives may also be offered.