ASIC Design Efficiency Engineer
Thomas To · Santa Clara, CA · Today
EngineeringFull-time
What You'll Be Doing
- Develop innovative HW, GPU and system designs to extend the state of the art performance and efficiency.
- Understand the design and implementation, develop methodology and infrastructure to drive Performance, Power and Area (PPA) improvements.
- Execute and deliver fully verified, high performance, area and power efficient RTL to achieve design targets.
- Collaborate with architects, designers, verification and VLSI teams to craft the industries' top performing GPUs.
What We Need To See
- Bachelors Degree in EE or CE or equivalent experience.
- 2+ years of experience.
- Proficiency in SystemVerilog or similar HDL.
- You have a solid understanding of logic design and computer architecture.
- Strong interpersonal skills are required along with the ability to work in a diverse product oriented team.
Ways To Stand Out From The Crowd
- Pipeline processor or deep learning accelerator design/architecture experience
- Performance verification, low power or physical (synthesis/VLSI) design experience
- Scripting knowledge in Python/Perl
Pay
Base salary range is 116,000 USD - 189,750 USD for Level 2, and 136,000 USD - 218,500 USD for Level 3. You will also be eligible for equity and benefits.