Analog IC Design and Verification Engineer

About the role

We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world.

The Brain Interfaces SoC Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future.

Responsibilities

• Design analog and mixed-signal chip components, from circuit design to layout and verification.
• Design analog circuit building blocks and subsystems at the transistor level to meet challenging noise, mismatch, distortion, power consumption, and cost requirements while satisfying top-level specifications.
• Work with layout teams to oversee block-level layout of multiple blocks.
• Plan and execute analog verification plans for portions of IP or chip, running complex simulations and analyses (e.g., power, performance, linearity, yield).
• Design, program, and run complex tests; review tests of junior team members to ensure bugs and issues are identified and analyzed.
• Consult with internal or external users and third-party vendors to guide implementation and ensure alignment with their needs.

Requirements

• Bachelor of Science degree and at least 5 years of additional experience in a related technical field after receiving the BS degree.
• Minimum 5 years of experience in analog/mixed-signal integrated CMOS circuit design for specific areas (e.g., delta-sigma ADC, SAR ADC, DAC, VCO, PLL, DLL, Audio CODEC and Class D audio amplifier, high-speed PHY & SERDES) with a successful track record of silicon validation.

The ideal candidates are people who get excited about building things, are highly analytical, and enjoy tackling new problems regularly.

Preferred Qualifications

• Masters or PhD in electrical engineering, physics, or other related fields.
• Experience with design for high-volume production.
• Experience in lab testing of high-precision analog and mixed-signal ICs.
• Functional modeling experience and logic verification with Verilog AMS and SystemVerilog.
• Experience in design and layout with advanced CMOS FinFET technologies.
• Skills in scripting and automation for complex simulation scenarios.

Pay

The anticipated base salary for this position is expected to be within the range of $125,000 USD - $291,000 USD. In addition to base salary, Neuralink offers equity compensation in the form of Restricted Stock Units (RSUs) for all full-time employees.

Benefits

• Full-time employees are eligible for the following benefits:
  • Excellent medical, dental, and vision insurance through a PPO plan.
  • Paid holidays.
  • Commuter benefits.
  • Meals provided.
  • Equity (RSUs).
  • 401(k) plan (after 1,000 hours for interns).
  • Parental leave.
  • Flexible time off.
• An opportunity to change the world and work with some of the smartest and most talented experts from different fields.
• Growth potential; we rapidly advance team members who have an outsized impact.