Analog IC Design Engineer

About the role

WaveWorks makes wireless communication solutions for the next wave of connected devices. WaveWorks' unique technology provides extremely low cost, small form factor, and orders of magnitude lower power consumption, while achieving long operating range and high reliability. WaveWorks is expanding its engineering team and searching for high performing, dedicated individuals to help blaze new trails. Role Description: WaveWorks designs wireless endpoint chips whose power budget is measured in nanoamps. The Analog Design Engineer designs, simulates and verifies the analog and mixed-signal blocks of these chips, where every block is judged first by the current it draws. The work sits on the company's current architectural charter: reducing active and sleep power far below what conventional radios achieve, while keeping range and reliability. This is a hands-on individual-contributor role on a small silicon team. The engineer owns blocks from specification through tapeout and silicon bring-up, and works closely with digital design, verification, and system architecture. With its unique technology, WaveWorks is positioned to meet the needs of a plethora of applications of wireless connectivity that are not well served by conventional wireless solutions. Join us as we work to capture this opportunity and become a significant force in wireless.

Responsibilities

• Design ultra-low-power analog and mixed-signal blocks: bias and reference generation, low-dropout regulators and power switches, oscillators and PLLs, and control loops.
• Design at nanoamp bias currents and low signal levels, managing leakage, noise, offset and mismatch across process, voltage and temperature.
• Define power domains and power-management behavior for always-on, duty-cycled operation, with an energy budget for each block.
• Build SystemVerilog and Verilog-AMS behavioral models of analog blocks, and run block-level and chip-level mixed-signal simulation with the digital design.
• Drive layout for low leakage and matching, and review parasitic-extracted results.
• Characterize silicon in the lab, correlate measurements with simulation, and feed results into the next revision.

Requirements

• BS in Electrical Engineering plus 5 or more years of analog IC design experience, MS plus 3 or more years, or a PhD degree.
• Proven record of taking analog blocks through tapeout in a CMOS process, and bringing them up on silicon.
• Fluency with Cadence Virtuoso and Spectre, or equivalent tools, including corner and Monte Carlo analysis.
• Mixed-signal (AMS) design and verification experience, including SystemVerilog and Verilog-AMS or real-number models for block-level and chip-level simulation.
• Strong command of subthreshold design, leakage, noise, and mismatch.
• Ability to write clear block specifications and work across analog, digital and verification teams.