AI Silicon, Design Verification

Responsibilities

• Define, architect, and implement comprehensive verification plans and environments for IP blocks and full chip from specification to tape-out.
• Help build verification infrastructure from ground zero to flexible and nimble environments, able to move quickly and scale for growth.
• Take full ownership of the verification lifecycle, including the development and maintenance of scalable testbenches, sophisticated test cases, and robust verification environments.
• Deploy industry-standard methodologies (UVM/SystemVerilog) to conduct constrained-random stimulus generation, coverage-driven verification, and assertions.
• Collaborate closely with digital and analog design teams, as well as software and systems teams, to define verification requirements, debug complex hardware/software interactions, and ensure design integrity.
• Perform exhaustive analysis of functional and code coverage. Debug failures at the RTL and gate level to ensure 100% verification closure and high-quality silicon.

Requirements

• Education: Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• Experience: Minimum of 8 years of hands-on experience with advanced verification methodologies and languages, specifically UVM and SystemVerilog.
• Technical Expertise: Proven track record of developing and maintaining complex verification testbenches and automated test environments.
• Scripting Experience: Proficiency in scripting languages (e.g., Python, Shell, or Bash) for automation of verification flows and result analysis.
• Tool and Infrastructure Knowledge: Strong familiarity with general-purpose operating systems such as Linux, and industry standard tools from companies such as Cadence and Synopsys.

Qualifications

• Master's degree or Ph.D. in Electrical Engineering or Computer Science, with a specific emphasis on computer architecture (preferred).
• Expert-level knowledge of UVM architecture and high-level behavioral modeling (preferred).
• Experience with modern AI-driven code generation tools (preferred).

Skills

• Advanced verification methodologies and languages, specifically UVM and SystemVerilog.
• Proficiency in scripting languages (e.g., Python, Shell, or Bash).
• Strong familiarity with general-purpose operating systems such as Linux.
• Industry standard tools from companies such as Cadence and Synopsys.

Benefits

• A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.

Pay

Miscellaneous details about pay structure can be found in the job description or provided upon request.

Schedule

Miscellaneous details about work schedule can be found in the job description or provided upon request.