AI Silicon, Digital Design Engineer

About the role

Since 2022, AI has transformed industries like education and software development, highlighting the need for more efficient computation. At Unconventional, we aim to address this by building a new, more efficient computing foundation for AI. Our work involves rethinking traditional computing approaches to leverage semiconductor physics directly for neural network processing.

Responsibilities

• Lead the detailed micro-architecture definition and top-level integration of digital blocks, including CPU, memory subsystems, and interfaces.
• Own for the integration of third-party IP into the main SoC fabric.
• Provide technical guidance and mentorship to junior digital design engineers.
• Contribute to setting best practices for design methodologies, code reviews, and quality assurance processes.
• Enhance and contribute to early stage design infrastructure for rapid tapeout.
• Drive and perform hands-on RTL design for complex, timing-critical SoC blocks and digital interfaces, ensuring power, performance, and area (PPA) targets are met.
• Implement and debug key digital interfaces.
• Perform initial synthesis and formal verification (LEC) to ensure the design is routable and meets frequency targets.
• Create block-level timing constraints.
• Run and resolve RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks using industry standard tools.
• Design Verification (DV) Support: Participate in the block-level verification plan and help develop a robust verification environment.
• Triage and debug complex simulation failures to ensure functional correctness.
• Facilitate seamless hand-off between internal design and internal or external physical implementation teams (synthesis, timing closure).

Requirements

• Education: B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: 8+ years of industry experience in digital ASIC/SoC design.
• Strong Technical Expertise: Expertise in Verilog RTL coding and digital design fundamentals.
• Design Flow Proficiency: Familiarity with standard EDA tools for simulation, synthesis, linting, and clock domain crossing (CDC) analysis.
• Understanding of the full ASIC design flow, from specification to tape-out.
• Communication: Excellent written and verbal communication skills.
• Leadership: Ability to lead junior engineers to achieve team goals, and to assist in the development of their skills.

Qualifications

• Experience with creating digital designs, including synchronous and asynchronous logic, state machines, and bus protocols.
• Experience developing scripts or tooling for design automation.
• Experience optimizing designs for performance, power, or area.
• Experience with modern design methods, including generative AI code development platforms.
• Experience with analog mixed signal technology and interfaces.

Skills

• Verilog RTL coding
• Digital design fundamentals
• EDA tools for simulation, synthesis, linting, and clock domain crossing (CDC) analysis
• Full ASIC design flow from specification to tape-out
• Technical leadership and mentoring
• Hands-on RTL design
• RTL design for complex, timing-critical SoC blocks and digital interfaces
• Power, performance, and area (PPA) optimization
• Block-level timing constraints creation
• RTL linting, Clock Domain Crossing (CDC), and Reset Domain Crossing (RDC) checks
• Design Verification (DV) support
• Seamless hand-off between internal design and physical implementation teams

Benefits

A comprehensive package including best-in-class health benefits, 401k matching, truly unlimited PTO, and complimentary meals in our Palo Alto office.

Pay

Competitive salary commensurate with experience.

Schedule

Flexible work schedule to accommodate your needs.