Advanced ASIC FPGA Design Engineer for Crypto and Cross Domain Solutions

General Dynamics Mission Systems engineers a diverse portfolio of high technology solutions, products, and services that enable customers to successfully execute missions across all domains of operation.

About the role

Architect and implement high-performance FPGA designs targeting Xilinx and Microchip device families in an Agile development environment.

Responsibilities

• Architect and implement high-performance FPGA designs in VHDL and/or Verilog targeting Xilinx and Microchip device families.
• Perform synthesis, place-and-route, and timing closure using Vivado or Libero, including advanced techniques such as pipelining, register retiming, floorplanning, and physical optimization.
• Develop and execute block-level simulations using QuestaSim/ModelSim with code coverage analysis (statement, branch, condition, expression).
• Create self-checking testbenches for correctness verification.
• Design high-speed interfaces for inter-module communication and system integration.
• Collaborate with systems engineers, software developers, and verification engineers in an Agile development environment.
• Participate in design reviews, peer code reviews, and documentation of design specifications and interface control documents.
• Contribute to CI/CD pipeline development for automated synthesis, simulation regression, and coverage tracking.
• Support integration and lab bring-up activities, including on-target FPGA debug using ILAs and JTAG-based tools.

Requirements

• Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 5 years of relevant experience; or Master's degree plus a minimum of 3 years of relevant experience.
• Department of Defense Secret security clearance is required at time of hire. U.S. citizenship is required.

Qualifications

• Strong proficiency in VHDL and/or Verilog/SystemVerilog for synthesizable RTL design.
• Hands-on experience with Xilinx Vivado Design Suite or Microchip Libero for synthesis, implementation, and timing analysis.
• Experience targeting Xilinx and Microchip device families.
• Ability to achieve timing closure on designs at 300+ MHz clock rates.
• Experience with FPGA simulation tools (QuestaSim or ModelSim).
• Proficiency in writing self-checking testbenches with automated pass/fail determination.
• Understanding of high-speed digital design principles: pipelining, clock domain crossing (CDC), metastability mitigation, and synchronous design.
• Experience with AXI-Stream, AXI4, or similar on-chip bus protocols.
• Ability to read and interpret timing reports, utilization summaries, and critical-path analysis output.
• Strong written and verbal communication skills for design documentation and technical presentations.

Preferred Qualifications

• Experience with cryptographic algorithm implementation in hardware (AES, GCM, SHA, ECC, RSA, or similar).
• Experience with high-speed serial interfaces: PCIe, Ethernet (10G/25G/100G), Fibre Channel, Aurora, or GTY/GTM transceivers.
• Experience with CI/CD pipelines for FPGA development (GitLab CI) including automated synthesis and regression testing.
• Proficiency in scripting languages (Tcl, Python, Bash) for build automation and design flow scripting.
• Experience with version control systems (GitLab) and collaborative development workflows.
• Experience with Xilinx IP cores: FIFO Generator, Clock Wizard, MIG/DDR controllers, DMA/Bridge subsystems.
• Experience with embedded processors in FPGA (MicroBlaze, Zynq PS, Versal AI Engine).

Pay

Target salary range: USD $135,396.00/Yr. - USD $150,205.00/Yr.

Benefits

Highly competitive benefits including a flexible work environment where contributions are recognized and rewarded.