Verification Engineer, Emulation and Prototyping

About the role

Are you passionate about ASIC validation at NVIDIA? We're looking for hardworking systems engineers to craft verification and validation knowledge and extend it to emulation and FPGA environments for our next-generation GPUs, SOCs, NICs, and Switches. This role involves pushing the boundaries of innovation to make emulation and FPGA platforms faster, more scalable, and more efficient in a fast-paced, collaborative environment.

Responsibilities

• Build emulation and FPGA environments by making RTL FPGA/emulation-friendly, partitioning the design, and taking it through synthesis, place-and-route, and emulator compilation flows.
• Improve performance of emulation and FPGA platforms, analyze timing/performance bottlenecks, and generate bitstreams/images.
• Bring new DV test benches that provide high-level abstraction of C/SV testbenches, running at FPGA speeds.
• Bring up designs on hardware emulation and FPGA platforms and drive complex debug and problem-solving activities.
• Scale emulation/FPGA verification methodology to cater to extensive test plans.
• Work closely with architects, designers, verification engineers, validation teams, and software teams to accomplish project goals.
• Enable pre-silicon software development, validation, and performance analysis using hardware emulation and FPGA environments.
• Develop and optimize emulation-friendly validation infrastructures, including high-performance software interfaces and scalable debug methodologies.
• Develop efficient DPI/PLI/SystemC-based interfaces and software infrastructures that enable high-speed validation, debug, and bring-up on hardware emulation platforms.

Requirements

• BS (or equivalent experience) in Electrical Engineering, Computer Engineering, or related fields with 5+ years of experience, or MS with 3+ years of proven experience in FPGA prototyping and/or hardware emulation.
• Strong understanding of FPGA prototyping and hardware emulation architectures, devices, flows, and tools.
• Hands-on experience with simulators or emulators across vendors.
• Hands-on experience with emulation platforms such as Synopsys ZeBu, Siemens Veloce, or Cadence Z3.
• Familiarity with ProtoCompiler, Synplify Premier, or Xilinx Vivado.
• Extensive knowledge of writing SV/Verilog code for testbenches and high-speed integrations.
• Understanding of industry-standard protocols such as PCIe, CXL, NVLINK, USB, CHI, and CPU-GPU coherency.
• Strong expertise in crafting and optimizing emulation-friendly C/C++ testbenches and transactors that function efficiently at emulation speeds.
• Experience minimizing host-emulator communication bottlenecks and improving transaction efficiency.
• Ability to craft scalable validation environments based on software for high-performance SoCs and multi-ASIC systems.

Skills

• Ability to actively code in C/C++, Python, and Perl.
• Experience with hardware emulation or prototyping platforms (Synopsys HAPS, ZeBu, Siemens Veloce) of high-performance processors or SOCs is highly desirable.
• Understanding of performance-sensitive validation methodologies for large-scale emulation environments, including efficient logging, synchronization, memory handling, and protocol traffic generation.
• Experience enabling pre-silicon software validation, firmware bring-up, or system-level debug on emulation platforms is a plus.
• Understanding of Cadence/Synopsys/Siemens transactor solutions.

Pay

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is:

• 136,000 USD - 218,500 USD for Level 3
• 168,000 USD - 264,500 USD for Level 4

You will also be eligible for equity and benefits.