Design Verification and Emulation Manager

Key Responsibilities

• Define end-to-end verification strategy from block-level through full-chip simulation to emulation and prototyping
• Own UVM-based methodology, including constrained-random, coverage-driven closure, assertions, and formal verification adoption
• Drive emulation platform strategy — platform selection, capacity planning, compilation flows, and multi-project scheduling
• Enable system-level validation on emulation — processor boot, OS bring-up, firmware execution, and IO exercising
• Deliver pre-silicon platforms for early software development in partnership with firmware and software teams
• Establish hybrid simulation-emulation methodologies using transactor-based interfaces to maximize both environments
• Own functional coverage models and sign-off criteria, driving closure across simulation and emulation combined
• Lead debug and root cause analysis across simulation and emulation, driving cross-functional bug resolution
• Manage verification dashboards, bug tracking, and regression health to provide clear visibility to program leadership
• Build, mentor, and scale a high-performing team of verification and emulation engineers
• Drive verification schedules and risk mitigation aligned with chip program milestones and tapeout readiness
• Represent verification and emulation in tapeout readiness reviews and program-level decision forums
• Collaborate cross-functionally with Compiler Team, RTL design, architecture, DFT, physical design, and post-silicon teams
• Manage emulation lab infrastructure, including hardware resources, licensing, and vendor relationships
• Evaluate and adopt new EDA tools and methodologies, including AI/ML-assisted verification techniques.
• Define right DV mix for in-house vs outsourcing to 3rd party vendors. Coordinate 3rd party vendor resources towards achieving project goals.

Required Qualifications & Experience

• Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. PhD is a plus.
• Experience: 12+ years of progressive experience in ASIC/SoC design verification, with at least 3–5 years in a management or senior technical leadership role overseeing both verification and emulation functions.
• Verification Methodology: Deep expertise in UVM, constrained-random verification, functional coverage, assertions (SVA), and simulation-based debug. Strong understanding of formal verification techniques.
• Emulation Platforms: Hands-on experience with at least one major emulation platform (Palladium, ZeBu, or Veloce) and familiarity with FPGA prototyping flows.
• Languages & Tools: Strong proficiency in SystemVerilog, Verilog, and C/C++ for testbench and reference model development. Experience with Python, Tcl, and scripting for flow automation.
• SoC Architecture: Solid understanding of modern SoC architectures — processors (ARM, RISC-V), cache coherency, interconnects (AMBA AXI/ACE/CHI), memory subsystems, and common peripherals.
• Leadership: Demonstrated ability to build, mentor, and manage verification teams of 10+ engineers. Experience hiring, developing talent, and scaling teams.
• Execution: Strong track record of driving verification closure and tapeout sign-off on complex designs (multi-million gate, multi-clock domain, multi-power domain).

Preferred Qualification

• Experience with portable stimulus standard (PSS / Accellera) for verification reuse across simulation and emulation.
• Background in power-aware verification (UPF/CPF-based) and low-power design verification challenges.
• Experience with AI/ML-assisted verification techniques (e.g., intelligent coverage convergence, ML-driven regression optimization).