Verification Engineer
Saicon · Austin, TX · 1 mo ago
On-siteInformation TechnologyContract
About the role
Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence). Strong proficiency in System Verilog Assertions (SVA) and formal property specification.
Qualifications
- Extensive experience in design verification with a strong focus on formal verification
- Experience with formal verification applications: FPV, connectivity checking, register verification, equivalence checking, and coverage analysis
- Familiarity with scripting languages (TCL, Python, Perl) for flow automation
Skills
- Expertise in System Verilog and UVM-based verification methodologies (Nice to have)