Verification Engineer

About the role

HII Mission Technologies is seeking out-of-the-box thinkers who can uncover difficult-to-activate corner-case bugs and vulnerabilities in the gate-level netlists of FPGA and ASIC designs. Candidates will develop models, transactors, stimuli, monitors, and test benches for simulating and uncovering hidden behaviors in gate-level digital netlists. They will produce clear documentation and test cases demonstrating identified bugs or deviations from the specification. Collaboration with teammates to produce cohesive results and create improved processes is essential.

Responsibilities

• Develop models, transactors, stimuli, monitors, and test benches for simulating and uncovering hidden behaviors in gate-level digital netlists.
• Produce clear documentation and test cases demonstrating identified bugs or deviations from the specification.
• Collaborate with teammates to produce cohesive results and create improved processes.

Requirements

• Level 2: 2 years relevant experience with Bachelors in related field; 0 years experience with Masters in related field; or High School Diploma or equivalent and 6 years relevant experience.
• Level 3 : 5 years relevant experience with Bachelors in related field; 3 years relevant experience with Masters in related field; 0 years experience with PhD or Juris Doctorate in related field; or High School Diploma or equivalent and 9 years relevant experience.
• Level 4 : 9 years relevant experience with Bachelors in related field; 7 years relevant experience with Masters in related field; 4 years relevant experience with PhD or Juris Doctorate in realted field; or High School Diploma or equivalent and 13 years relevant experience.
• Level 5 : 15 years relevant experience with Bachelors in related field; 13 years relevant experience with Masters in related field; 10 years relevant experience with PhD or Juris Doctorate in related field; or High School Diploma or equivalent and 19 years relevant experience.

Qualifications

• Experience with modern digital verification and modeling languages: SystemVerilog, SystemC, C/C++, Matlab, etc.
• Directed, constrained-random, and assertion-based verification techniques at the gate, interface, and transaction levels.
• Experience with modern, commercial-grade, functional simulators (e.g., Xcelium, Incisive, Questa, VCS, Riviera-Pro, etc).
• Writing scripts for batched verification tasks: Python, Bash, Tcl, make files.
• Revision control systems for maintaining, sharing, and deploying code: Perforce, git, SVN, etc.
• Familiarity with debugging and isolating issues with gate-level netlists.

Skills

• Familiarity with object-oriented, embedded, assembly, or machine code programming.
• Software or hardware reverse-engineering (e.g., IDA Pro, Ghidra).
• FPGA design or verification.
• Active Top Secret security clearance.
• Familiarity with testing and verification techniques for IC trust, assurance, or security.
• Experience with logical equivalence checkers (e.g., OneSpin 360-EC, ESP, Conformal EC).
• Experience with formal ABV.

Benefits

• Best-in-class medical, dental and vision plan choices.
• Wellness resources.
• Employee assistance programs.
• Savings Plan Options (401(k)).
• Financial planning tools, life insurance.
• Employee discounts.
• Paid holidays and paid time off.
• Tuition reimbursement.
• Early childhood and post-secondary education scholarships.

Pay

The anticipated salary range for this role is $72,497.00 - $246,509.00.

Schedule

Full Time/Salaried/Exempt.