Verification Engineer

Key Responsibilities

• Create, implement, and maintain RTL verification environments using UVM or equivalent methodologies
• Create and execute coverage-driven verification plans aligned with design specifications
• Develop directed and constrained-random test cases and sequences to validate functionality and identify corner cases
• Analyze simulation results, debug complex verification and design issues, and perform root-cause analysis in collaboration with RTL design engineers
• Implement and track functional and code coverage, driving verification to closure
• Develop reusable verification components and write SystemVerilog Assertions (SVA)
• Participate in design and verification reviews, providing input on design testability, correctness, and optimization
• Automate regression testing and enhance verification infrastructure using Python and scripting
• Contribute to continuous improvement of verification processes, tools, and methodologies

Required Skills And Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
• 7+ years of experience in digital design verification
• Strong hands-on experience with UVM-based or similar verification methodologies
• Proficiency in SystemVerilog, UVM, and Python
• Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)
• Solid understanding of digital design fundamentals
• Experience verifying standard bus and interconnect protocols such as AXI, AXI-S, and APB
• Experience with high-speed communication protocols including PCIe, Ethernet (10G/40G/100G), SPI, and I²C
• Strong analytical and problem-solving skills
• Clear written and verbal communication skills for cross-functional collaboration
• High attention to detail and ability to deliver reliable, high-quality verification outcomes
• Able to work independently and manage tasks to completion

Desired Skills

• Experience with formal verification techniques and tools
• Experience verifying processor subsystems or SoC-level designs