Verification Engineer

About the role

You verify the blocks and subsystems of a first-of-its-kind chiplet — building UVM testbenches, writing tests, and driving coverage to closure. Guided by the verification plan and methodology, you take assigned blocks from testbench bring-up through coverage signoff, and help debug across simulation and emulation.

Responsibilities

• Build and extend UVM testbenches (agents, sequences, scoreboards) for assigned blocks and subsystems.
• Write directed and constrained-random tests; develop functional coverage and drive it to closure.
• Verify the in-house engines against an algorithmic golden model, with programmable error injection and error-pattern coverage.
• Integrate and use VIP (e.g., UCIe) and run compliance, link-training, loopback, and lane-repair scenarios.
• Run regressions, triage failures, and help maintain the CI/regression flow.
• Register (UVM RAL) verification, firmware co-simulation, and boot flows on the MCU subsystem.
• Mixed-signal co-simulation — verifying digital blocks against behavioral / real-number models of analog/mixed-signal blocks.
• Support hardware-assisted verification — bring up and run tests on emulation / FPGA prototyping.
• Participate in gate-level and low-power (UPF) verification during signoff.
• Collaborate with the design, architecture, modelling, and DFT teams as your blocks move through the flow.

Requirements

• BS or MS in Electrical/Computer Engineering (or equivalent experience).
• 3+ years of ASIC/SoC functional verification.
• Solid UVM/SystemVerilog; constrained-random and coverage-driven verification.
• Testbench development and coverage closure — building block/subsystem testbenches and driving functional + code coverage to closure.
• Strong debug skills across simulation; scripting in Python, Perl, or TCL.
• Familiarity with regression/CI flows and failure triage.

Preferred

• High-speed SerDes, PAM4, or FEC/coding (Reed-Solomon) verification.
• UCIe, PCIe/CXL, Ethernet, or UALink VIP / compliance experience.
• Mixed-signal verification (Verilog-AMS or SV real-number models).
• Hardware-assisted verification — emulation (e.g., Palladium/Veloce) and/or FPGA prototyping (e.g., HAPS/Protium).
• Low-power/UPF and gate-level simulation; performance-verification methodology.
• Exposure to NICs, Ethernet/IB switches, or cache-coherent fabrics (multi-core / coherent fabric).
• Formal verification for control/interlock logic; portable stimulus.

Benefits

Competitive salary commensurate with experience
Comprehensive benefits package including health, dental, and vision
Professional development opportunities and certification support
Access to cutting-edge technology and cloud platforms
Collaborative work environment with cross-functional teams

Pay

Commensurate with experience

Schedule

N/A