Verification Engineer

About the role

Our client is seeking a Verification Engineer to join their team. As a Verification Engineer, you will be part of the Design Verification Department supporting innovative projects and collaborative teams. The ideal candidate will demonstrate strong analytical skills, proactive problem-solving abilities, and excellent communication skills, which will align successfully in the organization.

Location: Austin, TX

Responsibilities

• Perform formal verification using VC Formal (Synopsys) and/or Jasper Gold (Cadence) tools to ensure design correctness.
• Develop and maintain System Verilog Assertions (SVA) and formal property specifications for complex hardware modules.
• Apply formal verification applications such as FPV, connectivity checking, register verification, and coverage analysis to validate design integrity.
• Automate verification flows using scripting languages like TCL, Python, or Perl to improve efficiency and accuracy.
• Collaborate with design and verification teams to identify issues early and implement effective solutions.

Requirements

• Hands-on experience with VC Formal (Synopsys) and/or Jasper Gold (Cadence) tools.
• Strong proficiency in System Verilog Assertions (SVA) and formal property specification.
• Experience with formal verification applications including FPV, connectivity checking, register verification, and coverage analysis.
• Familiarity with scripting languages such as TCL, Python, or Perl for flow automation.
• Extensive experience in design verification with a focus on formal verification methodologies.

Benefits

• Opportunity to work on cutting-edge verification projects in a dynamic environment.
• Collaborate with talented professionals and expand your technical expertise.
• Engage in continuous learning and professional development.
• Contribute to innovative solutions that impact the industry.
• Be part of a supportive and inclusive work culture that values diversity and inclusion.